Inventor
KUMAR SHISHIR
IN34 patents
⚠️ This page may combine multiple inventors who share the name “KUMAR SHISHIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS INT NV
17 patentsUS10283191B1May 7, 2019
Method and circuit for adaptive read-write operation in self-timed memory
ST MICROELECTRONICS INT NV6 citations83
US11532633B2Dec 20, 2022
Dual port memory cell with improved access resistance
ST MICROELECTRONICS INT NV1 citations72
US11152376B2Oct 19, 2021
Dual port memory cell with improved access resistance
ST MICROELECTRONICS INT NV1 citations72
US11742045B2Aug 29, 2023
Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
ST MICROELECTRONICS INT NV2 citations70
US10998077B2May 4, 2021
Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
ST MICROELECTRONICS INT NV3 citations70
US11889675B2Jan 30, 2024
Dual port memory cell with improved access resistance
ST MICROELECTRONICS INT NV0 citations62
US9165642B2Oct 20, 2015
Low voltage dual supply memory cell with two word lines and activation circuitry
ST MICROELECTRONICS INT NV2 citations62
US11025252B2Jun 1, 2021
Circuit for detection of single bit upsets in generation of internal clock for memory
ST MICROELECTRONICS INT NV0 citations58
US11521697B2Dec 6, 2022
Circuit and method for at speed detection of a word line fault condition in a memory circuit
ST MICROELECTRONICS INT NV0 citations51
US11195576B2Dec 7, 2021
Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier
ST MICROELECTRONICS INT NV0 citations51
US10706915B2Jul 7, 2020
Method and circuit for adaptive read-write operation in self-timed memory
ST MICROELECTRONICS INT NV0 citations51
US9147453B2Sep 29, 2015
Programmable delay introducing circuit in self timed memory
ST MICROELECTRONICS INT NV0 citations51
US10311944B2Jun 4, 2019
SRAM read multiplexer including replica transistors
ST MICROELECTRONICS INT NV0 citations50
US10037794B1Jul 31, 2018
SRAM read multiplexer including replica transistors
ST MICROELECTRONICS INT NV0 citations50
US11393532B2Jul 19, 2022
Circuit and method for at speed detection of a word line fault condition in a memory circuit
ST MICROELECTRONICS INT NV0 citations49
US9590602B2Mar 7, 2017
System and method for a pulse generator
ST MICROELECTRONICS INT NV0 citations41
US9324414B2Apr 26, 2016
Selective dual cycle write operation for a self-timed memory
ST MICROELECTRONICS INT NV0 citations40
SYNOPSYS INC
6 patentsUS12316326B1May 27, 2025
Delay circuit
SYNOPSYS INC0 citations62
US12272424B2Apr 8, 2025
Reducing spurious write operations in a memory device
SYNOPSYS INC0 citations62
US12094513B2Sep 17, 2024
Power supply tracking circuitry for embedded memories
SYNOPSYS INC0 citations62
US12354656B2Jul 8, 2025
Reducing memory device bitline leakage
SYNOPSYS INC0 citations52
US12112818B2Oct 8, 2024
Scan chain compression for testing memory of a system on a chip
SYNOPSYS INC0 citations52
US12340864B2Jun 24, 2025
Interface level-shifter dual-rail memory architecture
SYNOPSYS INC0 citations50
WIPRO LTD
3 patentsUS10191902B2Jan 29, 2019
Method and unit for building semantic rule for a semantic data
WIPRO LTD3 citations72
US10073838B2Sep 11, 2018
Method and system for enabling verifiable semantic rule building for semantic data
WIPRO LTD2 citations72
US9898527B2Feb 20, 2018
Methods for retrieving information and devices thereof
WIPRO LTD0 citations41