Inventor

TETELBAUM ALEXANDER

US49 patents

⚠️ This page may combine multiple inventors who share the name “TETELBAUM ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TETELBAUM ALEXANDER

LSI LOGIC CORP

Integrated design system and method for reducing and avoiding crosstalk

Method of clock driven cell placement and clock tree synthesis for integrated circuit design

Method for estimating porosity of hardmacs

Method of clock buffer partitioning to minimize clock skew for an integrated circuit design

Integrated circuit design system and method for reducing and avoiding crosstalk

Method of automated repair of crosstalk violations and timing violations in an integrated circuit design

Method for estimating cell porosity of hardmacs

Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction

Wire delay distributed model

Integrated design system and method for reducing and avoiding crosstalk

Method of finding critical nets in an integrated circuit design

Method for minimizing clock skew for an integrated circuit

Intelligent crosstalk delay estimator for integrated circuit design flow

Integrated circuit design flow with capacitive margin

Minimal bends connection models for wire density calculation

Method of noise analysis and correction of noise violations for an integrated circuit design

Method and apparatus for implementing a co-axial wire in a semiconductor chip

Method of control cell placement to minimize connection length and cell delay

Elmore model enhancement

Method of global placement of control cells and hardmac pins in a datapath macro for an integrated circuit design

Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit

Balanced clock placement for integrated circuits containing megacells

Intelligent engine for protection against injected crosstalk delay

Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees

Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints

Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism

Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design

Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring

Global chip interconnect

Method of control cell placement for datapath macros in integrated circuit designs

Pin placement method for integrated circuits

Method of datapath cell placement for an integrated circuit

TETELBAUM ALEXANDER

System and method for designing integrated circuits that employ adaptive voltage scaling optimization

Circuit timing analysis incorporating the effects of temperature inversion

Circuit timing analysis incorporating the effects of temperature inversion

Intelligent dummy metal fill process for integrated circuits

Reducing path delay sensitivity to temperature variation in timing-critical paths

Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing

Timing signoff system and method that takes static and dynamic voltage drop into account

Timing error sampling generator and a method of timing testing

Programmable slew rate power switch

Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same

LSI CORP

Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit

Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer

Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same

Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer

SANDISK TECHNOLOGIES INC

Systems, circuitry, and methods for decoding pulse width modulated signal

Charge pump with matched currents

MOLINA JR RUBEN SALVADOR

Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer