Inventor

SCHEIPER THILO

DE72 patents

⚠️ This page may combine multiple inventors who share the name “SCHEIPER THILO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHEIPER THILO

SCHEIPER THILO

Self-aligned fin transistor formed on a bulk substrate by late fin etch

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Contact bars with reduced fringing capacitance in a semiconductor device

Superior integrity of high-k metal gate stacks by capping STI regions

Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures

Workfunction metal stacks for a final metal gate

Source and drain architecture in an active region of a P-channel transistor by tilted implantation

Semiconductor device with dual metal silicide regions and methods of making same

Semiconductor element comprising a low variation substrate diode

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

FLACHOWSKY STEFAN

Methods of performing highly tilted halo implantation processes on semiconductor devices

Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same

Semiconductor device with strain-inducing regions and method thereof

Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy

Methods of forming stressed silicon-carbon areas in an NMOS transistor

Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy

Semiconductor device with strain-inducing regions and method thereof

Canyon gate transistor and methods for its fabrication

Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process

GLOBALFOUNDRIES INC

Work function adjustment in high-k gate stacks for devices of different threshold voltage

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

Work function adjustment in high-k gate stacks including gate dielectrics of different thickness

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

Full silicidation prevention via dual nickel deposition approach

Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

Metal gate structure for semiconductor devices

Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures

HOENTSCHEL JAN

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices

Strain memorization in strained SOI substrates of semiconductor devices

BEYER SVEN

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

WEI ANDY

Method for forming double gate and tri-gate transistors on a bulk substrate

Self-aligned multiple gate transistor formed on a bulk substrate

GLOBALFOUNDRIES SG PTE LTD

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

GRIEBENOW UWE

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

ADVANCED MICRO DEVICES INC

Recessed drain and source areas in combination with advanced silicide formation in transistors

JAVORKA PETER

Full silicidation prevention via dual nickel deposition approach

BAARS PETER

Method of forming contacts for devices with multiple stress liners