Inventor
ECKEL NATHAN A
US21 patents
⚠️ This page may combine multiple inventors who share the name “ECKEL NATHAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
13 patentsUS9171597B2Oct 27, 2015
Apparatuses and methods for providing strobe signals to memories
MICRON TECHNOLOGY INC8 citations83
US9437263B2Sep 6, 2016
Apparatuses and methods for providing strobe signals to memories
MICRON TECHNOLOGY INC3 citations72
US11074131B2Jul 27, 2021
Storage backed memory package save trigger
MICRON TECHNOLOGY INC1 citations71
US11070375B2Jul 20, 2021
Key encryption handling
MICRON TECHNOLOGY INC4 citations71
US10642695B2May 5, 2020
Storage backed memory package save trigger
MICRON TECHNOLOGY INC2 citations71
US10984881B1Apr 20, 2021
Memory sub-system self-testing operations
MICRON TECHNOLOGY INC2 citations70
US12511192B2Dec 30, 2025
Information broadcast techniques for stacked memory architectures
MICRON TECHNOLOGY INC0 citations62
US12443354B2Oct 14, 2025
Boot and initialization techniques for stacked memory architectures
MICRON TECHNOLOGY INC0 citations62
US11579791B2Feb 14, 2023
Partial save of memory
MICRON TECHNOLOGY INC0 citations61
US11579979B2Feb 14, 2023
Storage backed memory package save trigger
MICRON TECHNOLOGY INC0 citations61
US10831393B2Nov 10, 2020
Partial save of memory
MICRON TECHNOLOGY INC1 citations61
US11514995B2Nov 29, 2022
Memory sub-system self-testing operations
MICRON TECHNOLOGY INC0 citations60
US11650925B2May 16, 2023
Memory interface management
MICRON TECHNOLOGY INC0 citations47
UNISYS CORP
7 patentsUS6996645B1Feb 7, 2006
Method and apparatus for spawning multiple requests from a single entry of a queue
UNISYS CORP30 citations92
US7739451B1Jun 15, 2010
Method and apparatus for stacked address, bus to memory data transfer
UNISYS CORP34 citations91
US7051131B1May 23, 2006
Method and apparatus for recording and monitoring bus activity in a multi-processor environment
UNISYS CORP36 citations88
US7003628B1Feb 21, 2006
Buffered transfer of data blocks between memory and processors independent of the order of allocation of locations in the buffer
UNISYS CORP22 citations88
US7421545B1Sep 2, 2008
Method and apparatus for multiple sequence access to single entry queue
UNISYS CORP11 citations83
US7797472B2Sep 14, 2010
Method and apparatus for providing overlapping defer phase responses
UNISYS CORP2 citations62
US7827455B1Nov 2, 2010
System and method for detecting glitches on a high-speed interface
UNISYS CORP4 citations57