Inventor
VARTTI KELVIN S
US24 patents
Patents
24 patentsUS5678026AOct 14, 1997
Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues
UNISYS CORP155 citations98
US6993630B1Jan 31, 2006
Data pre-fetch system and method for a cache memory
UNISYS CORP54 citations95
US7496715B1Feb 24, 2009
Programmable cache management system and method
UNISYS CORP26 citations92
US7260677B1Aug 21, 2007
Programmable system and method for accessing a shared memory
UNISYS CORP31 citations92
US7120836B1Oct 10, 2006
System and method for increasing cache hit detection performance
UNISYS CORP33 citations92
US6816952B1Nov 9, 2004
Lock management system and method for use in a data processing system
UNISYS CORP33 citations92
US6625698B2Sep 23, 2003
Method and apparatus for controlling memory storage locks based on cache line ownership
UNISYS CORP41 citations92
US6374332B1Apr 16, 2002
Cache control system for performing multiple outstanding ownership requests
UNISYS CORP44 citations92
US5574753ANov 12, 1996
Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs
UNISYS CORP23 citations91
US6973541B1Dec 6, 2005
System and method for initializing memory within a data processing system
UNISYS CORP32 citations90
US7065614B1Jun 20, 2006
System and method for maintaining memory coherency within a multi-processor data processing system
UNISYS CORP15 citations84
US6973548B1Dec 6, 2005
Data acceleration mechanism for a multiprocessor shared memory system
UNISYS CORP17 citations83
US6928517B1Aug 9, 2005
Method for avoiding delays during snoop requests
UNISYS CORP13 citations83
US5422918AJun 6, 1995
Clock phase detecting system for detecting the phase difference between two clock phases regardless of which of the two clock phases leads the other
UNISYS CORP20 citations82
US6728835B1Apr 27, 2004
Leaky cache mechanism
UNISYS CORP16 citations81
US7299311B1Nov 20, 2007
Apparatus and method for arbitrating for a resource group with programmable weights
UNISYS CORP18 citations79
US7533223B1May 12, 2009
System and method for handling memory requests in a multiprocessor shared memory system
UNISYS CORP7 citations73
US7222222B1May 22, 2007
System and method for handling memory requests in a multiprocessor shared memory system
UNISYS CORP9 citations73
US6934810B1Aug 23, 2005
Delayed leaky write system and method for a cache memory
UNISYS CORP11 citations73
US5381416AJan 10, 1995
Detection of skew fault in a multiple clock system
UNISYS CORP19 citations73
US6697925B1Feb 24, 2004
Use of a cache ownership mechanism to synchronize multiple dayclocks
UNISYS CORP7 citations71
US7797472B2Sep 14, 2010
Method and apparatus for providing overlapping defer phase responses
UNISYS CORP2 citations62
US6799249B1Sep 28, 2004
Split control for IP read and write cache misses
UNISYS CORP2 citations62
US6857049B1Feb 15, 2005
Method for managing flushes with the cache
UNISYS CORP1 citations51