Inventor

LIU CHUNG-SHI

TW751 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHUNG-SHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHUNG-SHI

TAIWAN SEMICONDUCTOR MFG

Fan-out interconnect structure and method for forming same

Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby

Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby

Method of forming a smooth copper seed layer for a copper damascene structure

Copper chemical-mechanical-polishing (CMP) dishing

System and method for an improved fine pitch joint

Interconnect structures and methods of forming same

Directly sawing wafers covered with liquid molding compound

Method to improve copper process integration

Dual damascene patterned conductor layer formation method

Multi-step plasma process for forming TiSiN barrier

In-situ cleaning process for Cu metallization

Methods to improve copper-fluorinated silica glass interconnects

Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure

Dual damascene process

Method to improve copper via electromigration (EM) resistance

Dual damascene patterned conductor layer formation method without etch stop layer

Robust post Cu-CMP IMD process

Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage

Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer

Integrated structure in wafer level package

Interconnect structures for wafer level package and methods of forming same

Damascene method employing composite etch stop layer

Metal bond pad for low-k inter metal dielectric

Multi-step planarizing method for forming a patterned thermally extrudable material layer

Methods for edge alignment mark protection during damascene electrochemical plating of copper

Passivation method for copper process

Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming semiconductor packages having through package vias

Photoactive compound gradient photoresist

Package-on-package structure including a thermal isolation material and method of forming the same

Packages with molding structures and methods of forming the same

Redistribution structures in semiconductor packages and methods of forming same

Advanced structure for info wafer warpage reduction

Integrated devices in semiconductor packages and methods of forming same

Package-on-package structure and method

Package on-package structure

3D package structure and methods of forming same

Methods of packaging semiconductor devices and packaged semiconductor devices

Integrated fan-out (InFO) package structures and methods of forming same

Packages with molding structures and methods of forming the same

Methods of forming connector pad structures, interconnect structures, and structures thereof

Dicing in wafer level package

IMEC

Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer

YU CHEN-HUA

Package-on-package (PoP) structure including stud bulbs and method

LU WEN-HSIUNG

Cu pillar bump with electrolytic metal sidewall protection

HSU CHUN-LEI

Package on package devices and methods of packaging semiconductor dies

HWANG CHIEN LING

Cu pillar bump with non-metal sidewall spacer and metal top cap

LIN CHIH-WEI

Packaging methods and structures for semiconductor devices

CHENG MING-DA

Mechanisms for forming copper pillar bumps