Inventor

CIAVATTI JEROME

US35 patents

⚠️ This page may combine multiple inventors who share the name “CIAVATTI JEROME”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CIAVATTI JEROME

GLOBALFOUNDRIES INC

Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method

Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array

Two-port vertical SRAM circuit structure and method for producing the same

LDMOS FinFET structures with trench isolation in the drain extension

Methods of forming source/drain contact structures on integrated circuit products

Vertical SRAM structure

LDMOS finFET structures with multiple gate structures

Resistor and capacitor disposed directly upon a SAC cap of a gate structure of a semiconductor structure

Single diffusion break structure and cuts later method of making

Single diffusion break structure

Non-planar schottky diode and method of fabrication

Scaled memory structures or other logic devices with middle of the line cuts

LDMOS finFET structures with shallow trench isolation inside the fin

Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure

DRAM structure with a single diffusion break

Advanced faraday shield for a semiconductor device

SOI device structures with doped regions providing charge sinking

Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array

Multiple gate length device with self-aligned top junction

Transistor device with improved source/drain junction architecture and methods of making such a device

Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices

Methods of making a self-aligned channel drift device

Self-aligned channel drift device and methods of making such a device

Fin-type transistors with spacers on the gates

Non-planar vertical dual source drift metal-oxide semiconductor (VDSMOS)

Transistor device with improved source/drain junction architecture and methods of making such a device

Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices

Non-planar semiconductor structure with preserved isolation region

LDMOS fin-type field-effect transistors including a dummy gate

ST MICROELECTRONICS SA

Capacitor integration

DRAM and MOS transistor manufacturing

Dram bit lines

LIU YANXIANG

FINFET compatible PC-bounded ESD diode

MOREAU DAVID

Extended liner for localized thick copper interconnect