Inventor

LIN CHENG-TUNG

TW67 patents

⚠️ This page may combine multiple inventors who share the name “LIN CHENG-TUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN CHENG-TUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Metal liner overhang reduction and manufacturing method thereof

Vertical device having a protrusion source

Integrating junction formation of transistors with contact formation

Tunnel field-effect transistor

Method of forming a contact with a silicide region

Vertical device having a protrusion source

Vertical device having a protrusion structure

Methods for fabricating vertical-gate-all-around transistor structures

Method of making a silicide beneath a vertical structure

Vertical structure having an etch stop over portion of the source

Systems and methods for gap filling improvement

Vertical-gate-all-around devices and method of fabrication thereof

Formation method of interconnection structure of semiconductor device

Vertical device having a protrusion source

Contact with a silicide region

Contact structure and formation thereof

Contact with a silicide region

Method of forming isolation layer

Semiconductor device with multiple threshold voltage and method of fabricating the same

Method of forming isolation layer

Method of forming isolation layer

Semiconductor device and method of forming vertical structure

Systems and methods for gap filling improvement

Semiconductor device with multiple threshold voltage and method of fabricating the same

TAIWAN SEMICONDUCTOR MFG

Method of forming a vertical device

Robust dual damascene process

Semiconductor structure including silicide regions and method of making same

Method of forming silicided gate structure

Aperture width reduction method for forming a patterned photoresist layer

Semiconductor device and method of forming vertical structure

Structure and method for a CMOS device with doped conducting metal oxide as the gate electrode

Hybrid metal fully silicided (FUSI) gate

Contact structure and formation thereof

Methods for wet clean of oxide layers over epitaxial layers

Silicide formation with a pre-amorphous implant

Systems and methods for reducing contact resistivity of semiconductor devices

Methods for forming MOS devices with metal-inserted polysilicon gate stack

Semiconductor device with multiple silicide regions

Method for silicide formation on semiconductor devices

(unassigned)

Handle for kitchen utensil

Handle for kitchen utensil

Kitchenware organizer

Handle for kitchen utensil

NAT SCIENCE COUNCIL

Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films

Low temperature formation of palladium silicided shallow junctions using implant through metal/silicide technology

LIN CHENG-TUNG

Holder

MOSFETs having stacked metal gate electrodes and method

XU JEFF J

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

LIU CHUNG-SHI

Transistors with metal gate and methods for forming the same

YU CHEN-HUA

Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices