Inventor

YU CHEN-HUA

TW1,960 patents

⚠️ This page may combine multiple inventors who share the name “YU CHEN-HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU CHEN-HUA

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated fan-out package including voltage regulators and methods forming same

Multi-stack package-on-package structures

Tri-layer CoWoS structure

Stacked semiconductor devices and methods of forming same

Multi-stack package-on-package structures

Packages formed using RDL-last process

System on integrated chips and methods of forming same

Packages with Si-substrate-free interposer and method forming same

Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias

Integrated circuit package and method of forming same

Package structure and method

Package structure, semiconductor chip and method of fabricating the same

Multi-stack package-on-package structures

Semiconductor device and method

Semiconductor packages and methods of forming same

Semiconductor packages and methods of forming the same

Semicondcutor package

Package structures and methods of forming the same

Semiconductor package and method of forming the same

Fan-out stacked system in package (SIP) and the methods of making the same

Package structure and method of forming the same

Semiconductor package structure having am antenna pattern and manufacturing method thereof

Dummy features in redistribution layers (RDLS) and methods of forming same

Three-dimensional integrated circuit structure

Method of forming semiconductor packages having through package vias

TAIWAN SEMICONDUCTOR MFG

Testing of semiconductor chips with microbumps

Fan-out interconnect structure and method for forming same

Package with metal-insulator-metal capacitor and method of manufacturing the same

Structure and method for 3D IC package

Fan-out package structure and methods for forming the same

Multi-die stacking using bumps with different sizes

Embedded wafer-level bonding approaches

Germanium FinFETs having dielectric punch-through stoppers

Fin field-effect transistors

Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process

Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby

Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby

Method of forming a smooth copper seed layer for a copper damascene structure

Method of recovering alignment marks after chemical mechanical polishing of tungsten

Copper chemical-mechanical-polishing (CMP) dishing

Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma

Nitride-oxide sidewall spacer for salicide formation

Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer

Deposit-etch-deposit ozone/teos insulator layer method

YU CHEN-HUA

Methods and apparatus of wafer level package for heterogeneous integration technology

Interconnect structure for wafer level package

Packages with passive devices and methods of forming the same

LIN JING-CHENG

3DIC stacking device and method of manufacture

CHANG CHENG-HUNG

FinFETs having dielectric punch-through stoppers

IMEC

Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer