Inventor

LI JIYUN

US27 patents

⚠️ This page may combine multiple inventors who share the name “LI JIYUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI JIYUN

MICRON TECHNOLOGY INC

Apparatuses and methods for managing row access counts

Apparatuses and methods for managing row access counts

Apparatuses and methods for tracking victim rows

Methods for row hammer mitigation and memory devices and systems employing the same

Apparatuses and methods for lossy row access counting

Apparatuses and methods for controlling steal rates

Apparatuses and methods for tracking victim rows

Integrated assemblies comprising folded-digit-line-configurations

Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation

Apparatuses and methods for controlling steal rates

Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure

Apparatuses and methods to encode column plane compression data

Integrated assemblies comprising twisted digit line configurations

Integrated assemblies having voltage sources coupled to shields and/or plate electrodes through capacitors

3D DRAM with multiple memory tiers and vertically extending digit lines

Apparatus with latch correction mechanism and methods for operating the same

Integrated assemblies having voltage sources coupled to shields and/or plate electrodes through capacitors

Memory array with access line control having a shunt sense line

Compression method for defect visibility in a memory device

Circuit for tracking access occurrences

Multi-level cells, and related arrays, devices, systems, and methods

Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors

Apparatuses and methods for single-ended sense amplifiers

Integrated assemblies

Systems, devices, and methods for efficient usage of IO section breaks in memory devices

LODESTAR LICENSING GROUP LLC

Methods for row hammer mitigation and memory devices and systems employing the same

Methods for row hammer mitigation and memory devices and systems employing the same