Inventor
THORSON GREGORY M
US36 patents
⚠️ This page may combine multiple inventors who share the name “THORSON GREGORY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GROQ INC
13 patentsUS11243880B1Feb 8, 2022
Processor architecture
GROQ INC15 citations94
US11170307B1Nov 9, 2021
Predictive model compiler for generating a statically scheduled binary with known resource constraints
GROQ INC9 citations94
US11868250B1Jan 9, 2024
Memory design for a processor
GROQ INC9 citations86
US11210594B1Dec 28, 2021
Processor compiler
GROQ INC7 citations84
US11625618B1Apr 11, 2023
Processor compiler
GROQ INC1 citations73
US11263129B1Mar 1, 2022
Processor architecture
GROQ INC3 citations73
US12411762B2Sep 9, 2025
Memory design for a processor
GROQ INC0 citations62
US12223436B2Feb 11, 2025
Processor compiler for scheduling instructions to reduce execution delay due to dependencies
GROQ INC0 citations62
US11875874B2Jan 16, 2024
Data structures with multiple read ports
GROQ INC0 citations62
US11868908B2Jan 9, 2024
Processor compiler for scheduling instructions to reduce execution delay due to dependencies
GROQ INC0 citations62
US11568275B1Jan 31, 2023
Processor compiler
GROQ INC0 citations62
US11216734B1Jan 4, 2022
Processor compiler
GROQ INC0 citations62
US11114138B2Sep 7, 2021
Data structures with multiple read ports
GROQ INC0 citations62
SILICON GRAPHICS INC
10 patentsUS7007097B1Feb 28, 2006
Method and system for covering multiple resourcces with a single credit in a computer system
SILICON GRAPHICS INC98 citations96
US6674720B1Jan 6, 2004
Age-based network arbitration system and method
SILICON GRAPHICS INC169 citations96
US6973559B1Dec 6, 2005
Scalable hypercube multiprocessor network for massive parallel processing
SILICON GRAPHICS INC19 citations92
US6795900B1Sep 21, 2004
Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system
SILICON GRAPHICS INC30 citations92
US6643764B1Nov 4, 2003
Multiprocessor system utilizing multiple links to improve point to point bandwidth
SILICON GRAPHICS INC39 citations92
US7248635B1Jul 24, 2007
Method and apparatus for communicating computer data from one point to another over a communications medium
SILICON GRAPHICS INC44 citations90
US7464115B2Dec 9, 2008
Node synchronization for multi-processor computer systems
SILICON GRAPHICS INC16 citations84
US6831924B1Dec 14, 2004
Variable mode bi-directional and uni-directional computer communication system
SILICON GRAPHICS INC18 citations82
US6339812B1Jan 15, 2002
Method and apparatus for handling invalidation requests to processors not present in a computer system
SILICON GRAPHICS INC7 citations72
US6578115B2Jun 10, 2003
Method and apparatus for handling invalidation requests to processors not present in a computer system
SILICON GRAPHICS INC4 citations61
CRAY RESEARCH INC
5 patentsUS6055618AApr 25, 2000
Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel
CRAY RESEARCH INC181 citations99
US5721921AFeb 24, 1998
Barrier and eureka synchronization architecture for multiprocessors
CRAY RESEARCH INC132 citations98
US5701416ADec 23, 1997
Adaptive routing mechanism for torus interconnection network
CRAY RESEARCH INC152 citations98
US5533198AJul 2, 1996
Direction order priority routing of packets between nodes in a networked system
CRAY RESEARCH INC103 citations98
US5659796AAug 19, 1997
System for randomly modifying virtual channel allocation and accepting the random modification based on the cost function
CRAY RESEARCH INC86 citations96
NVIDIA CORP
3 patentsUS11336476B2May 17, 2022
Scalable in-network computation for massively-parallel shared-memory processors
NVIDIA CORP2 citations72
US11171798B2Nov 9, 2021
Scalable in-network computation for massively-parallel shared-memory processors
NVIDIA CORP2 citations72
US11463272B2Oct 4, 2022
Scalable in-network computation for massively-parallel shared-memory processors
NVIDIA CORP0 citations61