Inventor

CHANG WENG

TW104 patents

⚠️ This page may combine multiple inventors who share the name “CHANG WENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG WENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device and method

Etching back and selective deposition of metal gate

Etching back and selective deposition of metal gate

Methods for pre-deposition treatment of a work-function metal layer

Semiconductor device with metal gate structure comprising work-function metal layer and work-fuction adjustment layer

Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby

Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby

Nanosheet field-effect transistor device and method of forming

Nanosheet field-effect transistor device and method of forming

In-situ formation of metal gate modulators

Transistor gate structures and methods of forming the same

Method for patterning a lanthanum containing layer

Semiconductor device and method

Semiconductor device and method

Work function control in gate structures

In-situ formation of metal gate modulators

Nanosheet field-effect transistor device and method of forming

Methods for threshold voltage tuning and structure formed thereby

Semiconductor device with profiled work-function metal gate electrode and method of making

Semiconductor device and method

Method for patterning a lanthanum containing layer

Semiconductor device with profiled work-function metal gate electrode and method of making

Methods for threshold voltage tuning and structures formed thereby

Semiconductor device and method

Method for patterning a lanthanum containing layer

TAIWAN SEMICONDUCTOR MFG

Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections

Multilayer interface in copper CMP for low K dielectric

Method to reduce the moisture content in an organic low dielectric constant material

Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials

High performance strained channel MOSFETs by coupled stress effects

Hillock inhibiting method for forming a passivated copper containing conductor layer

Method of reducing dishing and erosion using a sacrificial layer

Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials

Method to improve metal line adhesion by trench corner shape modification

Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film

Method of protecting a low-K dielectric material

Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects

Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer

Silicon layer for stopping dislocation propagation

Silicon layer for stopping dislocation propagation

Method of improving an etching profile in dual damascene etching

Chemical mechanical polish planarizing method with pressure compensating layer

Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity

N metal for FinFET

Methods for enhancing within-wafer CMP uniformity

Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation

Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer

TAIWAN SEMICONDUCTOR MANFACTUR

Method to reduce via poison in low-k Cu dual damascene by UV-treatment

Silicon oxycarbide and silicon carbonitride based materials for MOS devices

UNIV RUTGERS

Apparatus for making nanostructured ceramic powders and whiskers