Inventor
HOWARD JOHN S
US32 patents
⚠️ This page may combine multiple inventors who share the name “HOWARD JOHN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
28 patentsUS6813251B1Nov 2, 2004
Split Transaction protocol for a bus system
INTEL CORP65 citations96
US6792495B1Sep 14, 2004
Transaction scheduling for a bus system
INTEL CORP65 citations96
US7675871B2Mar 9, 2010
Split transaction protocol for a bus system
INTEL CORP11 citations93
US6771664B1Aug 3, 2004
Transaction scheduling for a bus system in a multiple speed environment
INTEL CORP20 citations93
US7702825B2Apr 20, 2010
Enhancements to universal serial bus (USB) suspend and resume operations
INTEL CORP22 citations92
US7228366B2Jun 5, 2007
Method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule
INTEL CORP30 citations92
US6684272B1Jan 27, 2004
Throughput enhancement for a universal host controller interface in a universal serial bus
INTEL CORP20 citations92
US6389501B1May 14, 2002
I/O peripheral device for use in a store-and-forward segment of a peripheral bus
INTEL CORP25 citations92
US6067591AMay 23, 2000
Method and apparatus for avoidance of invalid transactions in a bus host controller
INTEL CORP45 citations92
US7213096B2May 1, 2007
Operating a remote USB host controller
INTEL CORP34 citations91
US6748465B2Jun 8, 2004
Local bus polling support buffer
INTEL CORP34 citations89
US7007119B2Feb 28, 2006
System and method for supporting split transactions on a bus
INTEL CORP23 citations86
US7007110B2Feb 28, 2006
Nak throttling for USB host controllers
INTEL CORP14 citations84
US6678761B2Jan 13, 2004
Method and apparatus for budget development under universal serial bus protocol in a multiple speed transmission environment
INTEL CORP19 citations84
US6606674B1Aug 12, 2003
Method and apparatus for reducing circular list's thrashing by detecting the queues' status on a circular linked list
INTEL CORP18 citations84
US6952429B2Oct 4, 2005
Transaction scheduling for a bus system in a multiple speed environment
INTEL CORP10 citations74
US7028124B2Apr 11, 2006
Method and apparatus for dual queue head processing of interrupt endpoints
INTEL CORP9 citations73
US9892081B2Feb 13, 2018
Split transaction protocol for a bus system
INTEL CORP1 citations63
US9600436B2Mar 21, 2017
Split transaction protocol for a bus system
INTEL CORP1 citations63
US6629186B1Sep 30, 2003
Bus controller and associated device drivers for use to control a peripheral bus having at least one store-and-forward segment
INTEL CORP4 citations63
US6546018B1Apr 8, 2003
Digital system having a peripheral bus structure with at least one store-and-forward segment
INTEL CORP5 citations63
US10372491B2Aug 6, 2019
Execution context migration method and apparatus
INTEL CORP1 citations62
US12482436B2Nov 25, 2025
Technologies for selective frame update on a display
INTEL CORP0 citations60
US9558142B2Jan 31, 2017
Split transaction protocol for a bus system
INTEL CORP0 citations52
US7886087B2Feb 8, 2011
Split transaction protocol for a bus system
INTEL CORP0 citations52
US7512082B1Mar 31, 2009
Tracking transaction status for a bus system providing legacy bus compatibility
INTEL CORP1 citations52
US12586508B2Mar 24, 2026
Asynchronous display pixel data streaming over I/O connections
INTEL CORP0 citations51
US9407863B2Aug 2, 2016
System and method for processing visual information
INTEL CORP0 citations42