Inventor

ORLOWSKI MARIUS K

US60 patents

⚠️ This page may combine multiple inventors who share the name “ORLOWSKI MARIUS K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ORLOWSKI MARIUS K

FREESCALE SEMICONDUCTOR INC

Semiconductor device structure and method therefor

Method of forming a transistor having multiple channels

Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration

Semiconductor structure with different lattice constant materials and method for forming the same

Transistor having multiple channels

Method of forming semiconductor device having nanotube structures

Multi-channel transistor structure and method of making thereof

FinFET structure with contacts

Single transistor memory cell with reduced programming voltages

Low RC product transistors in SOI semiconductor process

Dual surface SOI by lateral epitaxial overgrowth

Method and apparatus for performance enhancement in an asymmetrical semiconductor device

Method of manufacturing SOI template layer

Transistor with immersed contacts and methods of forming thereof

Diffusion barrier for nickel silicides in a semiconductor fabrication process

Process for forming an electronic device including semiconductor fins

Method for removing a semiconductor layer

Method for making a semiconductor structure using silicon germanium

Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)

Process of forming an electronic device including a layer of discontinuous storage elements

Semiconductor process for forming stress absorbent shallow trench isolation structures

Method to control the gate sidewall profile by graded material composition

Laterally grown nanotubes and method of formation

Laterally grown nanotubes and method of formation

Semiconductor process with first transistor types oriented in a first plane and second transistor types oriented in a second plane

Method for producing two gates controlling the same channel

Method of making a planar double-gated transistor

Method for forming a semiconductor device having isolation regions

Single transistor memory cell with reduced recombination rates

Process for forming an electronic device including a fin-type transistor structure

Semiconductor device structure

Electronic device including a fin-type transistor structure and a process for forming the electronic device

Programmable fuse with silicon germanium

Charge storage structure formation in transistor with vertical channel region

Single transistor memory cell with reduced recombination rates

Method for forming a semiconductor device having a fin and structure thereof

Method for making a semiconductor structure using silicon germanium

Isolation trench perimeter implant for threshold voltage control

Method for forming a semiconductor device having a notched control electrode and structure thereof

Transistor devices with nano-crystal gate structures

MOS device with nano-crystal gate structure

Semiconductor device and method for regional stress control

Self correcting suppression of threshold voltage variation in fully depleted transistors

MOTOROLA INC

Process for forming an electrically programmable read-only memory cell

Field effect transistor having a gate dielectric with variable thickness

Process for forming field isolation

Process for forming field isolation

Process for forming a transistor with a nonuniformly doped channel

ORLOWSKI MARIUS K

Method and apparatus for mobility enhancement in a semiconductor device

Transistors with immersed contacts