Inventor

NARITA SUSUMU

JP54 patents

⚠️ This page may combine multiple inventors who share the name “NARITA SUSUMU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARITA SUSUMU

HITACHI LTD

Processor with an addressable address translation buffer operative in associative and non-associative modes

Data processor having an address translation buffer operable with variable page sizes

Data processor and data processing system having two translation lookaside buffers

Data processor and single-chip microcomputer with changing clock frequency and operating voltage

Microprocessor operating at high and low clok frequencies

Semiconductor integrated circuit apparatus

Data processor for implementing virtual pages using a cache and register

Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler

Cache memory employing dynamically controlled data array start timing and a microcomputer using the same

Translation lookaside buffer supporting multiple page sizes

Microprocessor having PC card interface

Semiconductor integrated circuit apparatus

Accessing exception handlers without translating the address

Semiconductor integrated circuit device

Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM

Data processor having two instruction registers connected in cascade and two instruction decoders

Data processor and data processor system having multiple modes of address indexing and operation

Microprocessor having a PC card type interface

Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT

Microprocessor capable of decoding two instructions in parallel

Semiconductor integrated circuit device

Logic LSI

Pipeline processor with prefetch circuit

Data processing system having a card type interface with assigned addressing

Data processing system having a PC card type interface with assigned addressing

Cache memory employing dynamically controlled data array start timing and a microprocessor using the same

Cache memory employing dynamically controlled data array start timing and a microcomputer using the same

Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same

Semiconductor memory device with address comparing functions

KAYABA INDUSTRY CO LTD

Input apparatus

Input apparatus

Input apparatus

Servo regulator

Fluid pressure pump motor

NARITA SUSUMU

Optical scanner and image forming apparatus including the same

Curvature correction device, optical scanning unit, and image forming apparatus

Housing, optical scanner, and image forming apparatus

Optical writing device and image forming apparatus

RENESAS TECH CORP

Processor for controlling substrate biases in accordance to the operation modes of the processor

Semiconductor integrated circuit apparatus

Substrate bias switching unit for a low power processor

RENESAS ELECTRONICS CORP

Substrate bias switching unit for a low power processor

Substrate bias switching unit for a low power processor

WATANABE KAZUNORI

Optical scanning device and image forming apparatus

Optical scanning device and image forming apparatus

TOTO LTD

Discharge lamp, discharge lamp sealing method, discharge lamp sealing device

RICOH CO LTD

Optical scanning device and image forming apparatus

HIGAKI HIDETO

Image forming apparatus

SAKAUE YOSHINOBU

Casing structure, optical scanner, and image forming apparatus

JOHNO HIROSHI

Optical scanning device and image forming apparatus