Inventor

KEPLER NICK

US31 patents

Patents

31 patents

US6037671AMar 14, 2000

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

ADVANCED MICRO DEVICES INC25 citations93

US6255214B1Jul 3, 2001

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

ADVANCED MICRO DEVICES INC38 citations93

US6165903ADec 26, 2000

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

ADVANCED MICRO DEVICES INC29 citations93

US6150243ANov 21, 2000

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

ADVANCED MICRO DEVICES INC46 citations93

US6143624ANov 7, 2000

Shallow trench isolation formation with spacer-assisted ion implantation

ADVANCED MICRO DEVICES INC42 citations93

US6130467AOct 10, 2000

Shallow trench isolation with spacers for improved gate oxide quality

ADVANCED MICRO DEVICES INC23 citations93

US6124183ASep 26, 2000

Shallow trench isolation formation with simplified reverse planarization mask

ADVANCED MICRO DEVICES INC25 citations93

US6074927AJun 13, 2000

Shallow trench isolation formation with trench wall spacer

ADVANCED MICRO DEVICES INC37 citations93

US6238986B1May 29, 2001

Formation of junctions by diffusion from a doped film at silicidation

ADVANCED MICRO DEVICES INC33 citations92

US6162689ADec 19, 2000

Multi-depth junction formation tailored to silicide formation

ADVANCED MICRO DEVICES INC22 citations92

US6156615ADec 5, 2000

Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions

ADVANCED MICRO DEVICES INC22 citations92

US6100145AAug 8, 2000

Silicidation with silicon buffer layer and silicon spacers

ADVANCED MICRO DEVICES INC47 citations92

US6096599AAug 1, 2000

Formation of junctions by diffusion from a doped film into and through a silicide during silicidation

ADVANCED MICRO DEVICES INC27 citations92

US6046104AApr 4, 2000

Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias

ADVANCED MICRO DEVICES INC30 citations92

US6030862AFeb 29, 2000

Dual gate oxide formation with minimal channel dopant diffusion

ADVANCED MICRO DEVICES INC30 citations92

US6239031B1May 29, 2001

Stepper alignment mark structure for maintaining alignment integrity

ADVANCED MICRO DEVICES INC39 citations91

US6514844B1Feb 4, 2003

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

ADVANCED MICRO DEVICES INC21 citations90

US6169005B1Jan 2, 2001

Formation of junctions by diffusion from a doped amorphous silicon film during silicidation

ADVANCED MICRO DEVICES INC16 citations84

US5970362AOct 19, 1999

Simplified shallow trench isolation formation with no polish stop

ADVANCED MICRO DEVICES INC17 citations84

US5970363AOct 19, 1999

Shallow trench isolation formation with improved trench edge oxide

ADVANCED MICRO DEVICES INC19 citations84

US6380047B1Apr 30, 2002

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

ADVANCED MICRO DEVICES INC9 citations74

US6204177B1Mar 20, 2001

Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal

ADVANCED MICRO DEVICES INC13 citations74

US5795820AAug 18, 1998

Method for simplifying the manufacture of an interlayer dielectric stack

ADVANCED MICRO DEVICES INC15 citations74

US6380040B1Apr 30, 2002

Prevention of dopant out-diffusion during silicidation and junction formation

ADVANCED MICRO DEVICES INC5 citations63

US6162699ADec 19, 2000

Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery

ADVANCED MICRO DEVICES INC2 citations63

US6090712AJul 18, 2000

Shallow trench isolation formation with no polish stop

ADVANCED MICRO DEVICES INC6 citations60

US6090713AJul 18, 2000

Shallow trench isolation formation with simplified reverse planarization mask

ADVANCED MICRO DEVICES INC5 citations60

KEPLER NICK

Patents

Stepper alignment mark structure for maintaining alignment integrity

Shallow trench isolation formation without planarization mask

Shallow trench isolation formation with reduced polish stop thickness

Shallow trench isolation formation with ion implantation

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

Shallow trench isolation formation with spacer-assisted ion implantation

Shallow trench isolation with spacers for improved gate oxide quality

Shallow trench isolation formation with simplified reverse planarization mask

Shallow trench isolation formation with trench wall spacer

Formation of junctions by diffusion from a doped film at silicidation

Multi-depth junction formation tailored to silicide formation

Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions

Silicidation with silicon buffer layer and silicon spacers

Formation of junctions by diffusion from a doped film into and through a silicide during silicidation

Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias

Dual gate oxide formation with minimal channel dopant diffusion

Stepper alignment mark structure for maintaining alignment integrity

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

Formation of junctions by diffusion from a doped amorphous silicon film during silicidation

Simplified shallow trench isolation formation with no polish stop

Shallow trench isolation formation with improved trench edge oxide

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal

Method for simplifying the manufacture of an interlayer dielectric stack

Prevention of dopant out-diffusion during silicidation and junction formation

Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery

Shallow trench isolation formation with no polish stop

Shallow trench isolation formation with simplified reverse planarization mask