Inventor

CHEONG HOICHI

US36 patents

⚠️ This page may combine multiple inventors who share the name “CHEONG HOICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEONG HOICHI

IBM

System and method for managing the execution of instruction groups having multiple executable instructions

Issuing instructions in a processor supporting out-of-order execution

Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched

Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache

Checkpoint table for selective instruction flushing in a speculative execution unit

Method and system for efficiently restoring a processor&#39;s execution state following an interrupt caused by an interruptible instruction

System and method for dispatching groups of instructions using pipelined register renaming

Mechanism for self-initiated instruction issuing and method therefor

Data processing system and method for capturing history buffer data

Concurrent execution of machine context synchronization operations and non-interruptible instructions

Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution

Method and system for memory updates within a multiprocessor data processing system

Apparatus and method for reducing the number of rename registers required in the operation of a processor

Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution

Dispatching instructions in a processor supporting out-of-order execution

Information handling system including a direct access set associative cache and method for accessing same

Method and apparatus for condensed history buffer

Method and apparatus for improved recovery of processor state using history buffer

Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions

Shared L2 support for inclusion property in split L1 data and instruction caches

System and method for error correction code generation

System and method for handling instructions occurring after an ISYNC instruction

Data processing system and method for completing out-of-order instructions

High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address

Instruction dispatch unit and method for mapping a sending order of operations to a receiving order

Method and system for speculatively issuing instructions

Data processing system and method for extending the time for execution of an instruction

Apparatus and method for selecting entries from an array

Mechanism for self-initiated instruction issuing and method therefor

System for controlling access to external cache memories of differing size

Method and apparatus for fast parallel determination of queue entries

INTEL CORP

Cache lock mechanism with speculative allocation

Cache lock mechanism with speculative allocation

Method to remove stale branch predictions for an instruction prior to execution within a microprocessor

MADDURI VENKATESWARA R

Instruction and logic to length decode X86 instructions

Processor power management based on class and content of instructions

Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction