Inventor
SIEK DAVID D
US13 patents
Patents
13 patentsUS6066870AMay 23, 2000
Single digit line with cell contact interconnect
MICRON TECHNOLOGY INC191 citations98
US6735132B2May 11, 2004
6F2 DRAM array with apparatus for stress testing an isolation gate and method
MICRON TECHNOLOGY INC58 citations95
US6496027B1Dec 17, 2002
System for testing integrated circuit devices
MICRON TECHNOLOGY INC50 citations95
US5986955ANov 16, 1999
Method and apparatus for hiding data path equilibration time
MICRON TECHNOLOGY INC83 citations94
US6590817B2Jul 8, 2003
6F2 DRAM array with apparatus for stress testing an isolation gate and method
MICRON TECHNOLOGY INC25 citations92
US6930503B2Aug 16, 2005
System for testing integrated circuit devices
MICRON TECHNOLOGY INC28 citations91
US6756805B2Jun 29, 2004
System for testing integrated circuit devices
MICRON TECHNOLOGY INC23 citations91
US6510533B1Jan 21, 2003
Method for detecting or repairing intercell defects in more than one array of a memory device
MICRON TECHNOLOGY INC21 citations89
US7180802B2Feb 20, 2007
Method of stress-testing an isolation gate in a dynamic random access memory
MICRON TECHNOLOGY INC4 citations73
US6870750B2Mar 22, 2005
DRAM array and computer system
MICRON TECHNOLOGY INC7 citations73
US5866928AFeb 2, 1999
Single digit line with cell contact interconnect
MICRON TECHNOLOGY INC9 citations73
US6167541ADec 26, 2000
Method for detecting or preparing intercell defects in more than one array of a memory device
MICRON TECHNOLOGY INC11 citations70
US6999362B2Feb 14, 2006
Method of stress-testing an isolation gate in a dynamic random access memory
MICRON TECHNOLOGY INC0 citations51