Inventor
LIN CHONG-MING
US32 patents
⚠️ This page may combine multiple inventors who share the name “LIN CHONG-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SEIKO EPSON CORP
23 patentsUS5655124AAug 5, 1997
Selective power-down for high performance CPU/system
SEIKO EPSON CORP153 citations99
US6256743B1Jul 3, 2001
Selective power-down for high performance CPU/system
SEIKO EPSON CORP68 citations97
US6430693B2Aug 6, 2002
Selective power-down for high performance CPU/system
SEIKO EPSON CORP53 citations96
US5787297AJul 28, 1998
Selective power-down for high performance CPU/system
SEIKO EPSON CORP61 citations96
US6163194ADec 19, 2000
Integrated circuit with hardware-based programmable non-overlapping-clock-edge capability
SEIKO EPSON CORP26 citations95
US7506185B2Mar 17, 2009
Selective power-down for high performance CPU/system
SEIKO EPSON CORP8 citations92
US7082543B2Jul 25, 2006
Selective power-down for high performance CPU/system
SEIKO EPSON CORP21 citations92
US6900682B2May 31, 2005
Clock generator with programmable non-overlapping-clock-edge capability
SEIKO EPSON CORP19 citations92
US6587952B2Jul 1, 2003
Selective power-down for high performance CPU/system
SEIKO EPSON CORP14 citations92
US6323711B2Nov 27, 2001
Clock generator with programmable non-overlapping-clock-edge-capability
SEIKO EPSON CORP18 citations92
US6653881B2Nov 25, 2003
Clock generator with programmable non-overlapping-clock-edge capability
SEIKO EPSON CORP11 citations81
US6489826B2Dec 3, 2002
Clock generator with programmable non-overlapping clock-edge capability
SEIKO EPSON CORP13 citations81
US5909377AJun 1, 1999
Method for manufacturing a power bus on a chip
SEIKO EPSON CORP12 citations81
US5806084ASep 8, 1998
Space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory
SEIKO EPSON CORP14 citations81
US5726904AMar 10, 1998
Power bus having power slits embodied therein and method for making the same
SEIKO EPSON CORP13 citations81
US6785761B2Aug 31, 2004
Selective power-down for high performance CPU/system
SEIKO EPSON CORP7 citations74
US7642832B2Jan 5, 2010
Clock generator with programmable non-overlapping-clock-edge capability
SEIKO EPSON CORP4 citations73
US6233721B1May 15, 2001
Power bus and method for generating power slits therein
SEIKO EPSON CORP4 citations73
US7352222B2Apr 1, 2008
Clock generator with programmable non-overlapping-clock-edge capability
SEIKO EPSON CORP2 citations62
US6842885B2Jan 11, 2005
Computer program product for defining slits in a bus on a chip
SEIKO EPSON CORP2 citations62
US6378120B2Apr 23, 2002
Power bus and method for generating power slits therein
SEIKO EPSON CORP2 citations62
US7516436B2Apr 7, 2009
Method for manufacturing a power bus on a chip
SEIKO EPSON CORP0 citations51
US7103867B2Sep 5, 2006
Method for manufacturing a power bus on a chip
SEIKO EPSON CORP0 citations51
QSPEED SEMICONDUCTOR INC
4 patentsUS7220661B1May 22, 2007
Method of manufacturing a Schottky barrier rectifier
QSPEED SEMICONDUCTOR INC30 citations92
US7227242B1Jun 5, 2007
Structure and method for enhanced performance in semiconductor substrates
QSPEED SEMICONDUCTOR INC21 citations88
US7655964B1Feb 2, 2010
Programmable junction field effect transistor and method for programming same
QSPEED SEMICONDUCTOR INC11 citations84
US7238976B1Jul 3, 2007
Schottky barrier rectifier and method of manufacturing the same
QSPEED SEMICONDUCTOR INC12 citations84
LOVOLTECH INC
3 patentsUS6774417B1Aug 10, 2004
Electrostatic discharge protection device for integrated circuits
LOVOLTECH INC26 citations93
US7075132B1Jul 11, 2006
Programmable junction field effect transistor and method for programming the same
LOVOLTECH INC13 citations84
US7009229B1Mar 7, 2006
Electrostatic discharge protection device for integrated circuits
LOVOLTECH INC14 citations84