Inventor
OH HWA-JOON
US19 patents
⚠️ This page may combine multiple inventors who share the name “OH HWA-JOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS6829682B2Dec 7, 2004
Destructive read architecture for dynamic random access memories
IBM19 citations91
US7058830B2Jun 6, 2006
Power saving in a floating point unit using a multiplier and aligner bypass
IBM21 citations89
US7137021B2Nov 14, 2006
Power saving in FPU with gated power based on opcodes and data
IBM19 citations84
US6914453B2Jul 5, 2005
Integrated logic and latch design with clock gating at static input signals
IBM18 citations83
US7290023B2Oct 30, 2007
High performance implementation of exponent adjustment in a floating point design
IBM13 citations82
US7245159B2Jul 17, 2007
Protecting one-hot logic against short-circuits during power-on
IBM7 citations74
US6510093B1Jan 21, 2003
Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines
IBM9 citations74
US7392270B2Jun 24, 2008
Apparatus and method for reducing the latency of sum-addressed shifters
IBM7 citations72
US7490119B2Feb 10, 2009
High speed adder design for a multiply-add based floating point unit
IBM5 citations63
US7447725B2Nov 4, 2008
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units
IBM3 citations63
US6587388B2Jul 1, 2003
Method and apparatus for reducing write operation time in dynamic random access memories
IBM5 citations63
US7149877B2Dec 12, 2006
Byte execution unit for carrying out byte instructions in a processor
IBM4 citations60
US7237163B2Jun 26, 2007
Leakage current reduction system and method
IBM3 citations58
US7469265B2Dec 23, 2008
Methods and apparatus for performing multi-value range checks
IBM0 citations50
US7406589B2Jul 29, 2008
Processor having efficient function estimate instructions
IBM0 citations41
DHONG SANG HOO
3 patentsUS8229989B2Jul 24, 2012
Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units
DHONG SANG HOO14 citations83
US8131795B2Mar 6, 2012
High speed adder design for a multiply-add based floating point unit
DHONG SANG HOO3 citations62
US8166085B2Apr 24, 2012
Reducing the latency of sum-addressed shifters
DHONG SANG HOO1 citations50