Inventor
CUMMINGS DAVID W
US19 patents
⚠️ This page may combine multiple inventors who share the name “CUMMINGS DAVID W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
14 patentsUS9606922B2Mar 28, 2017
Selection of post-request action based on combined response and input from the request source
IBM0 citations52
US9547597B2Jan 17, 2017
Selection of post-request action based on combined response and input from the request source
IBM0 citations52
US9442852B2Sep 13, 2016
Programmable coherent proxy for attached processor
IBM0 citations52
US9390013B2Jul 12, 2016
Coherent attached processor proxy supporting coherence state update in presence of dispatched master
IBM1 citations52
US9367458B2Jun 14, 2016
Programmable coherent proxy for attached processor
IBM0 citations52
US9256537B2Feb 9, 2016
Coherent attached processor proxy supporting coherence state update in presence of dispatched master
IBM0 citations52
US9251077B2Feb 2, 2016
Accelerated recovery for snooped addresses in a coherent attached processor proxy
IBM0 citations51
US9146872B2Sep 29, 2015
Coherent attached processor proxy supporting master parking
IBM0 citations51
US9135174B2Sep 15, 2015
Coherent attached processor proxy supporting master parking
IBM0 citations51
US8990513B2Mar 24, 2015
Accelerated recovery for snooped addresses in a coherent attached processor proxy
IBM0 citations51
US9323702B2Apr 26, 2016
Increasing coverage of delays through arbitration logic
IBM0 citations50
US9015024B2Apr 21, 2015
Enabling reuse of unit-specific simulation irritation in multiple environments
IBM0 citations42
US9009018B2Apr 14, 2015
Enabling reuse of unit-specific simulation irritation in multiple environments
IBM0 citations42
US9594654B2Mar 14, 2017
Generating and detecting hang scenarios in a partially populated simulation environment
IBM0 citations35
CUMMINGS DAVID W
3 patentsUS8117390B2Feb 14, 2012
Updating partial cache lines in a data processing system
CUMMINGS DAVID W8 citations82
US10394998B2Aug 27, 2019
Acceleration of memory walking sequences during simulation
CUMMINGS DAVID W3 citations65
US8095739B2Jan 10, 2012
Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation
CUMMINGS DAVID W1 citations49