Inventor

WAIT CHARLES D

US29 patents

⚠️ This page may combine multiple inventors who share the name “WAIT CHARLES D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WAIT CHARLES D

IBM

Pre-loading context states by inactive hardware thread in advance of context switch

Ensuring forward progress for nested translations in a memory management unit

Fault tolerant stability critical execution checking using redundant execution pipelines

Branch prediction with power usage prediction and control

Branch prediction with power usage prediction and control

Branch prediction with power usage prediction and control

Dynamic range adjusting floating point execution unit

Determining page size via page table cache

Data dependent instruction decode

Redundant execution of instructions in multistage execution pipeline during unused execution cycles

Unified translation miss queue for multiple address translation modes

Reducing translation latency within a memory management unit using external caching structures

Reducing translation latency within a memory management unit using external caching structures

Ensuring forward progress for nested translations in a memory management unit

Promotion of ERAT cache entries

Sleeping and waking-up address translation that conflicts with translation level of active page table walks

Power optimized prefetching in set-associative translation lookaside buffer structure

HICKEY MARK J

Floating point execution unit with fixed point functionality

Dynamic range adjusting floating point execution unit

Fault tolerant stability critical execution checking using redundant execution pipelines

Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address

Processing core with speculative register preprocessing in unused execution unit cycles

Performing vector multiplication

Programmable integrated processor blocks

Instruction predication using instruction address pattern matching

Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

FLEISCHER BRUCE M

Register file soft error recovery