Inventor

BAGHSORKHI SARA S

US65 patents

⚠️ This page may combine multiple inventors who share the name “BAGHSORKHI SARA S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAGHSORKHI SARA S

INTEL CORP

Coordination and increased utilization of graphics processors during inference

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Compute optimizations for low precision machine learning operations

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Compute optimizations for neural networks using bipolar binary weight

Compute optimizations for low precision machine learning operations

Specialized fixed function hardware for efficient convolution

Compute optimizations for low precision machine learning operations

Efficient sharing and compression expansion of data across processing systems

Compute optimization mechanism for deep neural networks

Compute optimizations for neural networks

Extend GPU/CPU coherency to multi-GPU cores

Loop vectorization methods and apparatus

Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory

Compute optimization mechanism for deep neural networks

Dynamic distributed training of machine learning models

Specialized fixed function hardware for efficient convolution

Compute optimizations for neural networks using ternary weight

Compute optimizations for low precision machine learning operations

Compute optimization mechanism for deep neural networks

Efficient sharing and compression expansion of data across processing systems

Extend GPU/CPU coherency to multi-GPU cores

Neural network optimization mechanism

Compute optimization mechanism for deep neural networks

Coordination and increased utilization of graphics processors during inference

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Extend GPU/CPU coherency to multi-GPU cores

Loop vectorization methods and apparatus

Methods and systems to vectorize scalar computer program loops having loop-carried dependences

Instruction to reduce elements in a vector register with strided access pattern

Methods and systems to vectorize scalar computer program loops having loop-carried dependences

Methods and systems to vectorize scalar computer program loops having loop-carried dependences

Coordination and increased utilization of graphics processors during inference

Compute optimizations for neural networks

Compute optimization mechanism for deep neural networks

Coordination and increased utilization of graphics processors during inference

Efficient sharing and compression expansion of data across processing systems

Extend GPU/CPU coherency to multi-GPU cores

Storage management for machine learning at autonomous machines

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Coordination and increased utilization of graphics processors during inference

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Neural network optimization mechanism

Compute optimizations for low precision machine learning operations

Compute optimizations for low precision machine learning operations

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Compute optimizations for low precision machine learning operations

BHARADWAJ JAYASHANKAR

Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register