Inventor

BARIK RAJKISHORE

US66 patents

⚠️ This page may combine multiple inventors who share the name “BARIK RAJKISHORE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARIK RAJKISHORE

INTEL CORP

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Machine learning sparse computation mechanism

Tool for facilitating efficiency in machine learning

Efficient thread group scheduling

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Compute optimizations for neural networks using bipolar binary weight

Specialized fixed function hardware for efficient convolution

Compute optimization mechanism for deep neural networks

Compute optimizations for neural networks

Autonomous machines through cloud, error corrections, and predictions

Extend GPU/CPU coherency to multi-GPU cores

Function callback mechanism between a central processing unit (CPU) and an auxiliary processor

Adaptive scheduling for task assignment among heterogeneous processor cores

Compute optimization mechanism for deep neural networks

Instructions and logic to perform floating point and integer operations for machine learning

Specialized fixed function hardware for efficient convolution

Compute optimizations for neural networks using ternary weight

Compute optimization mechanism for deep neural networks

Dynamic precision for neural network compute operations

Extend GPU/CPU coherency to multi-GPU cores

Machine learning sparse computation mechanism

Compute optimization mechanism for deep neural networks

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Extend GPU/CPU coherency to multi-GPU cores

Function callback mechanism between a Central Processing Unit (CPU) and an auxiliary processor

Training with adaptive runtime and precision profiling

Work stealing in heterogeneous computing systems

Compute optimizations for neural networks

Dynamic precision for neural network compute operations

Instructions and logic to perform floating point and integer operations for machine learning

Efficient thread group scheduling

Machine learning sparse computation mechanism

Instructions and logic to perform floating point and integer operations for machine learning

Compute optimization mechanism for deep neural networks

Machine learning sparse computation mechanism

Dynamic precision for neural network compute operations

Instructions and logic to perform floating point and integer operations for machine learning

Extend GPU/CPU coherency to multi-GPU cores

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Machine learning sparse computation mechanism

Compute optimization mechanism for deep neural networks

NI YANG

Method and apparatus to facilitate shared pointers in a heterogeneous platform

IBM

Compilation of unified parallel C-language programs

BARIK RAJKISHORE

Electronic coupons decision support and recommendation system