Inventor

NISHIKAWA MASATOSHI

JP56 patents

⚠️ This page may combine multiple inventors who share the name “NISHIKAWA MASATOSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NISHIKAWA MASATOSHI

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional flat NAND memory device including concave word lines and method of making the same

Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same

Bonded die assembly using a face-to-back oxide bonding and methods for making the same

Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional memory device containing capacitor pillars and methods of making the same

Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same

Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

Within array replacement openings for a three-dimensional memory device

Split memory cells with unsplit select gates in a three-dimensional memory device

Three-dimensional memory device containing drain-select-level air gap and methods of making the same

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same

Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same

Three-dimensional memory device containing bit line switches

Three-dimensional memory device containing bit line switches

Three-dimensional memory device containing inter-select-gate electrodes and methods of making the same

Three-dimensional memory device including different height memory stack structures and methods of making the same

Non-volatile memory array driven from both sides for performance improvement

Parallel memory operations in multi-bonded memory device

Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

Sub-block size reduction for 3D non-volatile memory

Boost converter in memory chip

Three-dimensional memory device including different height memory stack structures and methods of making the same

Three-dimensional memory device including three-dimensional bit line discharge transistors and method of making the same

Three-dimensional memory device containing dummy antenna diodes

Vertical resistor in 3D memory device with two-tier stack

Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same

Bonded die assembly using a face-to-back oxide bonding and methods for making the same

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same

Systems and methods for defining memory sub-blocks

SANDISK TECHNOLOGIES INC

Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device

Field effect transistor with elevated active regions and methods of manufacturing the same

3D semicircular vertical NAND string with recessed inactive semiconductor channel sections

Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof

Vertical resistor in 3D memory device with two-tier stack

Passive devices for integration with three-dimensional memory devices

Passive devices for integration with three-dimensional memory devices

Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices

WESTERN DIGITAL TECH INC

Three-dimensional phase change memory device including vertically constricted current paths and methods of manufacturing the same

Three-dimensional memory device including laterally constricted current paths and methods of manufacturing the same

NISHIKAWA MASATOSHI

Plastic scissors with metallic cutting inserts

Method of manufacturing scissors and scissors

FUKUDA MASAHIRO

Method of manufacturing semiconductor device