Inventor

LICAUSI NICHOLAS V

US35 patents

⚠️ This page may combine multiple inventors who share the name “LICAUSI NICHOLAS V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LICAUSI NICHOLAS V

GLOBALFOUNDRIES INC

Forming a diffusion break during a RMG process

Self aligned buried power rail

Method for manufacturing fully aligned via structures having relaxed gapfills

Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material

Method of forming complementary nano-sheet/wire transistor devices with same depth contacts

FINFET fin height control

Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

Etch profile control during skip via formation

Fully aligned via in ground rule region

Metallization levels and methods of making thereof

Line end structures for semiconductor devices

Interconnect structures with airgaps and dielectric-capped interconnects

Interconnects formed by a metal displacement reaction

Metal on metal multiple patterning

Via and skip via structures

Structure, method and system for measuring RIE lag depth

Metal on metal multiple patterning

Via and skip via structures

Interconnect structure having reduced resistance variation and method of forming same

Interconnects formed by a metal replacement process

Formation of IC structure with pair of unitary metal fins

Methods of forming conductive structures using a sacrificial liner layer

Methods of trimming nanowire structures

Methods of identifying space within integrated circuit structure as mandrel space or non-mandrel space

GLOBALFOUNDRIES US INC

Self aligned buried power rail

Self aligned buried power rail

Fully aligned via in ground rule region

Interconnect structures with airgaps arranged between capped interconnects

MASZARA WITOLD P

Methods of forming FinFET devices with alternative channel materials

Methods of forming FinFET devices with alternative channel materials

LICAUSI NICHOLAS V

Methods of forming SRAM devices using sidewall image transfer techniques

Methods of patterning features in a structure using multiple sidewall image transfer technique

IBM

Skip via for metal interconnects

PSIQUANTUM CORP

Method and structure to incorporate multiple low loss photonic circuit components