Inventor
FU FANGWEN
US30 patents
⚠️ This page may combine multiple inventors who share the name “FU FANGWEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
29 patentsUS11842423B2Dec 12, 2023
Dot product operations on sparse matrix elements
INTEL CORP4 citations86
US10554977B2Feb 4, 2020
Method and system of high throughput arithmetic entropy coding for video coding
INTEL CORP15 citations84
US10909653B2Feb 2, 2021
Power-based and target-based graphics quality adjustment
INTEL CORP1 citations72
US10506255B2Dec 10, 2019
MV/mode prediction, ROI-based transmit, metadata capture, and format detection for 360 video
INTEL CORP2 citations72
US10424082B2Sep 24, 2019
Mixed reality coding with overlays
INTEL CORP2 citations72
US10291925B2May 14, 2019
Techniques for hardware video encoding
INTEL CORP3 citations71
US12242846B2Mar 4, 2025
Supporting 8-bit floating point format operands in a computing architecture
INTEL CORP1 citations64
US12346694B2Jul 1, 2025
Register file for systolic array
INTEL CORP1 citations63
US12189571B2Jan 7, 2025
Dual pipeline parallel systolic array
INTEL CORP1 citations63
US12554489B2Feb 17, 2026
Supporting 8-bit floating point format operands in a computing architecture
INTEL CORP0 citations62
US12198222B2Jan 14, 2025
Architecture for block sparse operations on a systolic array
INTEL CORP0 citations62
US11423507B2Aug 23, 2022
Power-based and target-based graphics quality adjustment
INTEL CORP0 citations62
US11051038B2Jun 29, 2021
MV/mode prediction, ROI-based transmit, metadata capture, and format detection for 360 video
INTEL CORP0 citations62
US10924744B2Feb 16, 2021
Selective coding
INTEL CORP0 citations62
US12039000B2Jul 16, 2024
Matrix operation optimization mechanism
INTEL CORP0 citations61
US11977895B2May 7, 2024
Hierarchical thread scheduling based on multiple barriers
INTEL CORP1 citations61
US11729403B2Aug 15, 2023
Lossless pixel compression based on inferred control information
INTEL CORP0 citations61
US11593454B2Feb 28, 2023
Matrix operation optimization mechanism
INTEL CORP0 citations61
US12585590B2Mar 24, 2026
Broadcast asynchronous loads to shared local memory
INTEL CORP0 citations59
US10848779B2Nov 24, 2020
Temporal motion vector prediction control in video coding
INTEL CORP0 citations52
US10542279B2Jan 21, 2020
Temporal motion vector prediction control in video coding
INTEL CORP0 citations52
US10872441B2Dec 22, 2020
Mixed reality coding with overlays
INTEL CORP0 citations51
US10587875B2Mar 10, 2020
Coding tools for subjective quality improvements in video codecs
INTEL CORP0 citations51
US10402932B2Sep 3, 2019
Power-based and target-based graphics quality adjustment
INTEL CORP0 citations51
US12399685B2Aug 26, 2025
Systolic array having support for output sparsity
INTEL CORP0 citations50
US12596656B2Apr 7, 2026
Prefetch aware LRU cache replacement policy
INTEL CORP0 citations46
US10097833B2Oct 9, 2018
Method and system of entropy coding using look-up table based probability updating for video coding
INTEL CORP1 citations45
US10715818B2Jul 14, 2020
Techniques for hardware video encoding
INTEL CORP0 citations40
US10547839B2Jan 28, 2020
Block level rate distortion optimized quantization
INTEL CORP0 citations39