Inventor

HARATIPOUR NAZILA

US36 patents

Patents

36 patents

US11063131B2Jul 13, 2021

Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering

INTEL CORP31 citations94

US11264512B2Mar 1, 2022

Thin film transistors having U-shaped features

INTEL CORP6 citations86

US11171243B2Nov 9, 2021

Transistor structures with a metal oxide contact buffer

INTEL CORP11 citations85

US11138499B2Oct 5, 2021

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

INTEL CORP5 citations84

US11843058B2Dec 12, 2023

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

INTEL CORP3 citations73

US11417770B2Aug 16, 2022

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

INTEL CORP0 citations62

US12349442B2Jul 1, 2025

Thin film transistors having semiconductor structures integrated with 2D channel materials

INTEL CORP0 citations62

US12040378B2Jul 16, 2024

Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering

INTEL CORP0 citations62

US11843054B2Dec 12, 2023

Vertical architecture of thin film transistors

INTEL CORP1 citations62

US11777029B2Oct 3, 2023

Vertical transistors for ultra-dense logic and memory applications

INTEL CORP0 citations62

US11727260B2Aug 15, 2023

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

INTEL CORP0 citations62

US11626475B2Apr 11, 2023

Trench capacitor with extended dielectric layer

INTEL CORP1 citations62

US11532439B2Dec 20, 2022

Ultra-dense ferroelectric memory with self-aligned patterning

INTEL CORP1 citations62

US11527656B2Dec 13, 2022

Contact electrodes for vertical thin-film transistors

INTEL CORP1 citations62

US11522060B2Dec 6, 2022

Epitaxial layers on contact electrodes for thin- film transistors

INTEL CORP1 citations62

US12593486B2Mar 31, 2026

Dual contact process with selective deposition

INTEL CORP0 citations61

US12575170B2Mar 10, 2026

Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability

INTEL CORP0 citations61

US12568644B2Mar 3, 2026

Contact over active gate structures with trench contact layers for advanced integrated circuit structure fabrication

INTEL CORP0 citations61

US12170319B2Dec 17, 2024

Dual contact process with stacked metal layers

INTEL CORP0 citations61

US12119387B2Oct 15, 2024

Low resistance approaches for fabricating contacts and the resulting structures

INTEL CORP1 citations61

US11901400B2Feb 13, 2024

MFM capacitor and process for forming such

INTEL CORP0 citations61

US11769789B2Sep 26, 2023

MFM capacitor with multilayered oxides and metals and processes for forming such

INTEL CORP0 citations61

US12426342B2Sep 23, 2025

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

INTEL CORP0 citations59

US11923290B2Mar 5, 2024

Halogen treatment for NMOS contact resistance improvement

INTEL CORP0 citations59

US12439669B2Oct 7, 2025

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

INTEL CORP0 citations58

US12166122B2Dec 10, 2024

Field-effect transistor (FET) with self-aligned ferroelectric capacitor and methods of fabrication

INTEL CORP0 citations52

US11450750B2Sep 20, 2022

Thin-film transistors with vertical channels

INTEL CORP0 citations52

US12328927B2Jun 10, 2025

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

INTEL CORP0 citations51

US11980037B2May 7, 2024

Memory cells with ferroelectric capacitors separate from transistor gate stacks

INTEL CORP0 citations50

US11742407B2Aug 29, 2023

Multilayer high-k gate dielectric for a high performance logic transistor

INTEL CORP0 citations49

US12048165B2Jul 23, 2024

Ferroelectric capacitors and methods of fabrication

INTEL CORP0 citations48

HARATIPOUR NAZILA

Patents

Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering

Thin film transistors having U-shaped features

Transistor structures with a metal oxide contact buffer

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Vertical thin-film transistors between metal layers

Contact electrodes and dielectric structures for thin film transistors

Relaxor ferroelectric capacitors and methods of fabrication

Thin film transistors having U-shaped features

Vertical thin film transistors having self-aligned contacts

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Thin film transistors having semiconductor structures integrated with 2D channel materials

Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering

Vertical architecture of thin film transistors

Vertical transistors for ultra-dense logic and memory applications

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Trench capacitor with extended dielectric layer

Ultra-dense ferroelectric memory with self-aligned patterning

Contact electrodes for vertical thin-film transistors

Epitaxial layers on contact electrodes for thin- film transistors

Dual contact process with selective deposition

Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability

Contact over active gate structures with trench contact layers for advanced integrated circuit structure fabrication

Dual contact process with stacked metal layers

Low resistance approaches for fabricating contacts and the resulting structures

MFM capacitor and process for forming such

MFM capacitor with multilayered oxides and metals and processes for forming such

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Halogen treatment for NMOS contact resistance improvement

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Field-effect transistor (FET) with self-aligned ferroelectric capacitor and methods of fabrication

Thin-film transistors with vertical channels

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

Memory cells with ferroelectric capacitors separate from transistor gate stacks

Multilayer high-k gate dielectric for a high performance logic transistor

Ferroelectric capacitors and methods of fabrication