Inventor

PIERSON MATTHEW D

US38 patents

⚠️ This page may combine multiple inventors who share the name “PIERSON MATTHEW D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PIERSON MATTHEW D

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Multicore bus architecture with non-blocking high performance transaction credit system

Multicore, multibank, fully concurrent coherence controller

Multicore, multibank, fully concurrent coherence controller

Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion

Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC

Highly integrated scalable, flexible DSP megamodule architecture

Secure master and secure guest endpoint security firewall

Secure master and secure guest endpoint security firewall

Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems

Hazard detection and elimination for coherent endpoint allowing out-of-order execution

Highly integrated scalable, flexible DSP megamodule architecture

Multicore bus architecture with non-blocking high performance transaction credit system

Multicore bus architecture with non-blocking high performance transaction credit system

Coherence controller slot architecture allowing zero latency write commit

Secure master and secure guest endpoint security firewall

Slot/sub-slot prefetch architecture for multiple memory requestors

Multicore bus architecture with non-blocking high performance transaction credit system

Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels

Slot/sub-slot prefetch architecture for multiple memory requestors

Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels

Slot/sub-slot prefetch architecture for multiple memory requestors

Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect

Slot/sub-slot prefetch architecture for multiple memory requestors

Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems

Optimum cache access scheme for multi endpoint atomic access in a multicore system

Multi processor multi domain conversion bridge with out of order return buffering

Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect

Deadlock-avoiding coherent system on chip interconnect

Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion

Multi processor bridge with mixed Endian mode support

Distributed data return buffer for coherence system with speculative address support

CHIRCA KAI

Slot/sub-slot prefetch architecture for multiple memory requestors

Prefetch stream filter with FIFO allocation and stream direction prediction

PIERSON MATTHEW D

Prefetcher with arbitrary downstream prefetch cancelation

Double-buffered data storage to reduce prefetch generation stalls

ANDERSON TIMOTHY D

Prefetch address hit prediction to reduce memory access latency