Inventor

FLANNAGAN STEPHEN T

US38 patents

⚠️ This page may combine multiple inventors who share the name “FLANNAGAN STEPHEN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FLANNAGAN STEPHEN T

MOTOROLA INC

Delay locked loop for detecting the phase difference of two signals having different frequencies

Redundancy for a block-architecture memory

Write control for a memory using a delay locked loop

Synchronous memory having parallel output data paths

Delay locked loop for detecting the phase difference of two signals having different frequencies

Pipelined memory having synchronous and asynchronous operating modes

Memory architecture with sub-arrays

Integrated circuit memory having a fuse detect circuit and method therefor

Cascode sense AMP and column select circuit and method of operation

Latching ECL to CMOS input buffer circuit

Memory with column redundancy and localized column redundancy control signals

Bit line precharge on a column address change

Tri-state differential amplifier

Summation of address transition signals

Layout for noise reduction on a reference voltage

High performance output driver

Chip select speed-up circuit for a memory

ECL differential multiplexing circuit

High speed logic circuit with reduced quiescent current

Non-address transition detection memory with improved access time

Memory input buffer with hysteresis and dc margin

Write-drive data controller

Asynchronous row and column control

Reduced power sense amplifier

Buffer circuit, memory device, and integrated circuit for receiving digital signals

Memory having bit line load with automatic bit line precharge and equalization

BICMOS sense amplifier with reverse bias protection

Memory using distributed data line loading

BICMOS combined bit line load and write gate for a memory

Logic level shifting circuit with minimal delay

Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal

ECL logic gate with voltage protection

Circuit for enabling a transmission gate in response to predecoded signals

INTEL CORP

Multiple bit dynamic random-access memory

Byte-wide dynamic RAM with multiplexed internal buses

Multiple bit output dynamic random-access memory

Testing method and apparatus for dram

Multiple bit output dynamic random-access memory