Inventor
AMERASEKERA E AJITH
US13 patents
Patents
13 patentsUS6081002AJun 27, 2000
Lateral SCR structure for ESD protection in trench isolated technologies
TEXAS INSTRUMENTS INC96 citations98
US6040968AMar 21, 2000
EOS/ESD protection for high density integrated circuits
TEXAS INSTRUMENTS INC82 citations96
US6628493B1Sep 30, 2003
System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
TEXAS INSTRUMENTS INC22 citations92
US5949094ASep 7, 1999
ESD protection for high density DRAMs using triple-well technology
TEXAS INSTRUMENTS INC21 citations92
US5930094AJul 27, 1999
Cascoded-MOS ESD protection circuits for mixed voltage chips
TEXAS INSTRUMENTS INC51 citations91
US6143594ANov 7, 2000
On-chip ESD protection in dual voltage CMOS
TEXAS INSTRUMENTS INC40 citations90
US6137144AOct 24, 2000
On-chip ESD protection in dual voltage CMOS
TEXAS INSTRUMENTS INC27 citations90
US6530064B1Mar 4, 2003
Method and apparatus for predicting an operational lifetime of a transistor
TEXAS INSTRUMENTS INC20 citations89
US6469353B1Oct 22, 2002
Integrated ESD protection circuit using a substrate triggered lateral NPN
TEXAS INSTRUMENTS INC18 citations84
US6433392B1Aug 13, 2002
Electrostatic discharge device and method
TEXAS INSTRUMENTS INC12 citations73
US5804860ASep 8, 1998
Integrated lateral structure for ESD protection in CMOS/BiCMOS technologies
TEXAS INSTRUMENTS INC10 citations73
US5793083AAug 11, 1998
Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity
TEXAS INSTRUMENTS INC5 citations61
US7456477B2Nov 25, 2008
Electrostatic discharge device and method
TEXAS INSTRUMENTS INC1 citations51