Inventor

STEPHENS TAB A

US35 patents

⚠️ This page may combine multiple inventors who share the name “STEPHENS TAB A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEPHENS TAB A

FREESCALE SEMICONDUCTOR INC

Process of forming a non-volatile memory cell including a capacitor structure

Semiconductor device incorporating a defect controlled strained channel structure and method of making the same

Semiconductor device incorporating a defect controlled strained channel structure and method of making the same

Semiconductor structure with different lattice constant materials and method for forming the same

Die stack with optical TSVs

FinFET structure with contacts

Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

Confined spacers for double gate transistor semiconductor fabrication process

Optical backplane mirror

Integration of a MEMS beam with optical waveguide and deflection in two dimensions

Optical wafer and die probe testing

Communication system die stack

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

Method of forming a finFET and structure

Optical redundancy

Semiconductor structure pattern formation

Method for forming a semiconductor device having a silicide layer

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

Microelectronic assembly having a heat spreader for a plurality of die

Gate security feature

Method of forming a semiconductor device having a metal layer

Plasma enhanced nitride layer

Decoupled complementary mask patterning transfer method

Microelectronic assembly having a heat spreader for a plurality of die

Semiconductor device with selectively modulated gate work function

Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device

Optical die test interface with separate voltages for adjacent electrodes

Method of forming a via

MCSHANE MICHAEL B

Techniques for reducing inductance in through-die vias of an electronic assembly

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

PELLEY PERRY H

Stacked semiconductor devices

Semiconductor devices with nonconductive vias

MATHEW LEO

Method to improve source/drain parasitics in vertical devices

PHAM TIM V

Wirebond recess for stacked die