Inventor
CHIANG MEN-CHOW
US14 patents
⚠️ This page may combine multiple inventors who share the name “CHIANG MEN-CHOW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
8 patentsUS9378069B2Jun 28, 2016
Lock spin wait operation for multi-threaded applications in a multi-core computing environment
IBM11 citations83
US7117337B2Oct 3, 2006
Apparatus and method for providing pre-translated segments for page translations in segmented operating systems
IBM11 citations83
US7783858B2Aug 24, 2010
Reducing memory overhead of a page table in a dynamic logical partitioning environment
IBM17 citations82
US7318125B2Jan 8, 2008
Runtime selective control of hardware prefetch mechanism
IBM10 citations79
US7107431B2Sep 12, 2006
Apparatus and method for lazy segment promotion for pre-translated segments
IBM8 citations73
US8959286B2Feb 17, 2015
Hybrid storage subsystem with mixed placement of file contents
IBM3 citations62
US9727469B2Aug 8, 2017
Performance-driven cache line memory access
IBM0 citations51
US9626294B2Apr 18, 2017
Performance-driven cache line memory access
IBM1 citations51
CHIANG MEN-CHOW
3 patentsUS8413158B2Apr 2, 2013
Processor thread load balancing manager
CHIANG MEN-CHOW2 citations59
US8402470B2Mar 19, 2013
Processor thread load balancing manager
CHIANG MEN-CHOW2 citations59
US8146087B2Mar 27, 2012
System and method for enabling micro-partitioning in a multi-threaded processor
CHIANG MEN-CHOW1 citations50