Inventor

NORRIE CHRISTOPHER I W

US44 patents

⚠️ This page may combine multiple inventors who share the name “NORRIE CHRISTOPHER I W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NORRIE CHRISTOPHER I W

INTEGRATED DEVICE TECH

Multiservice switching system with distributed switch fabric

Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits

System and method for deskewing data transmitted through data lanes

Method and device for base address sorting and entry into base address registers

Programmably sliceable switch-fabric unit and methods of use

Binary base address search device and method

Device and method for address matching with post matching limit check and nullification

Binary base address sorting method and device with shift vector

Device and method for handling catastrophic routing

Device for concurrent limit validity check

Method and system for error correction over serial link

Programmably sliceable switch-fabric unit and methods of use

PMC SIERRA US INC

System and method for avoiding error mechanisms in layered iterative decoding

Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

Layer specific attenuation factor LDPC decoder

System and method for reduced memory storage in LDPC decoding

System and method for random noise generation

System and method for adaptive check node approximation in LDPC decoding

NORRIE CHRISTOPHER I W

Data aggregation system and method for deskewing data at selectable data rates

Multi-queue system and method for deskewing symbols in data streams

Error correction code system and method

BCH data correction system and method

System and method for generating locator polynomials

MICROSEMI STORAGE SOLUTIONS (US) INC

High quality log likelihood ratios determined using two-index look-up table

System and method for higher quality log likelihood ratios in LDPC decoding

System and method for accumulating soft information in LDPC decoding

Memory controller and integrated circuit device for correcting errors in data read from memory cells

MICHELONI RINO

Nonvolatile memory controller with concatenated error correction codes

Nonvolatile memory controller with error detection for concatenated error correction codes

Nonvolatile memory controller with two-stage error correction technique for enhanced reliability

AMDAHL CORP

Expedited execution of pipelined command having self-ordering operand processing requirements

Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture

System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size

MICROCHIP TECH INC

Method and apparatus for gather/scatter operations in a vector processor

Processor having switch instruction circuit

Method and apparatus for desynchronizing execution in a vector processor

RISE TECHNOLOGY COMPANY

Mechanism to simplify built-in self test of a control store unit

Instruction cache address generation technique having reduced delays in fetching missed data

MICROSEMI STORAGE SOLUTIONS US INC

System and method for lifetime specific LDPC decoding

MICROSEMI SOLUTIONS U S INC

Method and apparatus for layer-specific LDPC decoding

MICROSEMI SOLUTIONS (U S ) INC

Layer specific LDPC decoder

INTERGRATED DEVICE TECHNOLOGY

Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits

ZETTACOM INC

Method and system for error correction over serial link