Inventor

NIEL STEPHAN

FR45 patents

⚠️ This page may combine multiple inventors who share the name “NIEL STEPHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NIEL STEPHAN

ST MICROELECTRONICS ROUSSET

Method for biasing an embedded source plane of a non-volatile memory having vertical select gates

Hot-carrier injection programmable memory and method of programming such a memory

Nonvolatile memory cells with a vertical selection gate of variable depth

Integrated circuit with vertically structured capacitive element, and its fabricating process

Co-integrated vertically structured capacitive element and fabrication process

Co-integrated vertically structured capacitive element and fabrication process

Structure and method of forming a semiconductor device

Compact non-volatile memory device of the type with charge trapping in a dielectric interface

Memory cell comprising non-self-aligned horizontal and vertical control gates

Method for forming a PN junction and associated semiconductor device

Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device

Memory cell comprising non-self-aligned horizontal and vertical control gates

Non-volatile memory with vertical selection transistors

Integrated circuit with vertically structured capacitive element, and its fabricating process

Integrated circuit with vertically structured capacitive element, and its fabricating process

Co-integrated vertically structured capacitive element and fabrication process

Method of reading and writing nonvolatile memory cells

Method for manufacturing an electronic device

Integrated filler capacitor cell device and corresponding manufacturing method

Compact non-volatile memory device of the type with charge trapping in a dielectric interface

Memory cell comprising non-self-aligned horizontal and vertical control gates

Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device

Twin memory cell interconnection structure

Method for manufacturing an EEPROM cell

Method for programming a split-gate memory cell and corresponding memory device

Vertical memory cell with non-self-aligned floating drain-source implant

Method of manufacturing a non-volatile memory

STMICROELECTRONICS ROUSSET

Memory cell comprising non-self-aligned horizontal and vertical control gates

Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor

Individually read-accessible twin memory cells

Dual non-volatile memory cell comprising an erase transistor

Method for programming a non-volatile memory cell comprising a shared select transistor gate

Vertical memory cell with non-self-aligned floating drain-source implant

Vertical memory cell with non-self-aligned floating drain-source implant

Memory cell having a vertical selection gate formed in an FDSOI substrate

Integrated circuit protected from short circuits caused by silicide

Twin memory cell interconnection structure

Dual non-volatile memory cell comprising an erase transistor

Memory cell having a vertical selection gate formed in an FDSOI substrate

ST MICROELECTRONICS CROLLES 2 SAS

Device of physically unclonable function with transistors, and manufacturing method

Method for manufacturing an electronic device

Integrated circuit with improved resistive region

Integrated circuit with improved resistive region

COMMISSARIAT ENERGIE ATOMIQUE

Device comprising multiple gate structures and method of simultaneously manufacturing different transistors

NIEL STEPHAN

Integrated circuit of decreased size