Inventor

AVILA CHRIS

US63 patents

⚠️ This page may combine multiple inventors who share the name “AVILA CHRIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AVILA CHRIS

SANDISK TECHNOLOGIES INC

In-situ block folding for nonvolatile memory

Bad block reconfiguration in nonvolatile memory

Pseudo block operation mode in 3D NAND

Write scheme for charge trapping memory

Three-dimensional NAND memory with adaptive erase

Block structure profiling in three dimensional memory

Non-volatile memory with efficient programming

Proxy wordline stress for read disturb detection

Zoned erase verify in three dimensional nonvolatile memory

Systems and methods for read disturb management in non-volatile memory

Pseudo block operation mode in 3D NAND

In-situ block folding for nonvolatile memory

Bad block reconfiguration in nonvolatile memory

Adaptive operation of three dimensional memory

Update block programming order

Selection of data for redundancy calculation in three dimensional nonvolatile memory

String dependent parameter setup

Sensing parameter management in non-volatile memory storage system to compensate for broken word lines

Efficient post write read in three dimensional nonvolatile memory

Select transistor tuning

Systems and methods for partial page programming of multi level cells

Detecting programmed word lines based on NAND string current

Compensation for sub-block erase

System and method to update read voltages in a non-volatile memory in response to tracking data

Pseudo block operation mode in 3D NAND

System for handling erratic word lines for non-volatile memory

Detecting programmed word lines based on NAND string current

Back gate operation with elevated threshold voltage

Optimized configurable NAND parameters

Optimized page programming order for non-volatile memory

System and method of determining reading voltages of a data storage device

Selection of data for redundancy calculation by likely error rate

Write scheme for charge trapping memory

Write operations for defect management in nonvolatile memory

Three-dimensional NAND memory with adaptive erase

Lower page only host burst writes

Block refresh to adapt to new die trim settings

Identification and operation of sub-prime blocks in nonvolatile memory

Inspection of non-volatile memory for disturb effects

SANDISK TECHNOLOGIES LLC

Read scrub with adaptive counter management

Techniques for reducing read disturb in partially written blocks of non-volatile memory

Proxy wordline stress for read disturb detection

Dynamic memory recovery at the sub-block level

Weighted read scrub for nonvolatile memory including memory holes

HUANG JIANMIN

Data transfer flows for on-chip folding

Non-volatile memory with multi-gear control using on-chip folding of data

SPROUSE STEVEN

Optimized page programming order for non-volatile memory

Method and system for achieving die parallelism through block interleaving

AVILA CHRIS

Scrub techniques for use with dynamic read

DUSIJA GAUTAM ASHOK

Non-volatile memory and method with post-write read and adaptive re-write to manage errors