Inventor

LEE ERIC N

US64 patents

⚠️ This page may combine multiple inventors who share the name “LEE ERIC N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE ERIC N

MICRON TECHNOLOGY INC

Semiconductor device structures including staircase structures, and related methods and electronic systems

Data path with clock-data tracking

Memory plane access management

Methods of forming semiconductor device structures

Apparatus and methods for programming memory cells using multi-step programming pulses

Memory sub-system sanitization

Memory devices with backside bond pads under a memory array

Semiconductor device structures, semiconductor devices, and electronic systems

Memory devices with distributed block select for a vertical string driver tile architecture

Memory device including dynamic programming voltage

Wave pipeline

Intervallic dynamic start voltage and program verify sampling in a memory sub-system

Multiple write programming for a segment of a memory device

Write-once memory encoded data

Volatile data storage in NAND memory

Status polling based on die-generated pulsed signal

Validating read level voltage in memory devices

Workload-based scan optimization

Resumption of program or erase operations in memory

Memory sub-system sanitization

Parallelized defect detection across multiple sub-blocks in a memory device

Memory devices for multiple read operations

Quick charge loss mitigation using two-pass controlled delay

Data burst suspend mode using multi-level signaling

Concurrent page cache resource access in a multi-plane memory device

Workload-based scan optimization

Status polling based on die-generated pulsed signal

Memory plane access management

Resumption of program or erase operations in memory

Memory devices for multiple read operations

Memory device including dynamic programming voltage

Cache release command for cache reads in a memory sub-system

Semiconductor devices including staircase structures

Resumption of program or erase operations in memory

Wave pipeline

Apparatus for programming memory cells using multi-step programming pulses

Memory devices with distributed block select for a vertical string driver tile architecture

Cache release command for cache reads in a memory sub-system

Devices including dummy regions, and related memory devices and electronic systems

Wave pipeline

Memory device programming technique for increased bits per cell

Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same

Memory device programming technique for increased bits per cell

Data burst queue management

Memory devices for suspend and resume operations

Intervallic dynamic start voltage and program verify sampling in a memory sub-system

Program refresh with gate-induced drain leakage

Double single level cell program in a memory device

LODESTAR LICENSING GROUP LLC

Memory devices with backside bond pads under a memory array

Memory devices with backside bond pads under a memory array