Inventor

WOJEWODA IGOR

US38 patents

⚠️ This page may combine multiple inventors who share the name “WOJEWODA IGOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOJEWODA IGOR

MICROCHIP TECH INC

Programmable pin designation for semiconductor devices

Maintaining input and/or output configuration and data state during and when coming out of a low power mode

Layout technique for a matching capacitor array using a continuous top electrode

Capacitor array arrangement for improving capacitor array matching

Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor

Phase locked loop with fast start-up circuitry

Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode

Analog-to-digital converter offset and gain calibration using internal voltage references

Layout technique for a capacitor array using continuous upper electrodes

Fault tolerant clock monitor system

Analog-to-digital conversion with micro-coded sequencer

Stack pointer with post increment/decrement allowing selection from parallel read/write address outputs

Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor

Master-slave latches and post increment/decrement operations

Boot sequencing for multi boot devices

Dithering circuit for serial data transmission

Dual boot panel SWAP mechanism

Multi-processor core device with MBIST

Flexible clocking for audio sample rate converter in a USB system

Temperature compensated clock frequency monitor

Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock

Dynamic peripheral function remapping to external input-output connections of an integrated circuit device

Method for powering down unused configuration bits to minimize power consumption

Circuit for powering down unused configuration bits to minimize power consumption

Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction

Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction

Method for manipulating a stack pointer with post increment/decrement operation

Low-pin microcontroller device with multiple independent microcontrollers

Minimizing switchover time in a hot swappable program memory

Integrity monitor peripheral for microcontroller and processor input/output pins

Enabling special modes within a digital device

Bit manipulation capable direct memory access

Low-pin microcontroller device with multiple independent microcontrollers

BOWLING STEPHEN

Scheduling events in a microprocessor using a plurality of delta time registers arranged as a sequence buffer and indicating a sequence position of the sequence buffer to process an event

High resolution pulse width modulation (PWM) frequency control using a tunable oscillator

BOMMENA SUDHIR

Programmable cyclic redundancy check CRC unit

WOJEWODA IGOR

Compact disc stand

PHOENIX TIM

Power optimization when using external clock sources