Inventor
MATLOCK DYER A
US11 patents
Patents
11 patentsUS5071792ADec 10, 1991
Process for forming extremely thin integrated circuit dice
HARRIS CORP177 citations96
US5185292AFeb 9, 1993
Process for forming extremely thin edge-connectable integrated circuit structure
HARRIS CORP81 citations94
US4624749ANov 25, 1986
Electrodeposition of submicrometer metallic interconnect for integrated circuits
HARRIS CORP63 citations94
US5429958AJul 4, 1995
Process for forming twin well CMOS integrated circuits
HARRIS CORP24 citations92
US5247199ASep 21, 1993
Process for forming twin well CMOS integrated circuits
HARRIS CORP26 citations92
US4829359AMay 9, 1989
CMOS device having reduced spacing between N and P channel
HARRIS CORP19 citations73
US4908683AMar 13, 1990
Technique for elimination of polysilicon stringers in direct moat field oxide structure
HARRIS CORP11 citations72
US4716071ADec 29, 1987
Method of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect lines
HARRIS CORP11 citations72
US4713260ADec 15, 1987
Method of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect lines
HARRIS CORP10 citations72
US4702000AOct 27, 1987
Technique for elimination of polysilicon stringers in direct moat field oxide structure
HARRIS CORP8 citations72
US4814285AMar 21, 1989
Method for forming planarized interconnect level using selective deposition and ion implantation
HARRIS CORP13 citations71