Inventor
CHHAGAN VIJAI KUMAR
SG5 patents
Patents
5 patentsUS6337262B1Jan 8, 2002
Self aligned T-top gate process integration
CHARTERED SEMICONDUCTOR MFG90 citations96
US6387765B2May 14, 2002
Method for forming an extended metal gate using a damascene process
CHARTERED SEMICONDUCTOR MFG19 citations92
US6391732B1May 21, 2002
Method to form self-aligned, L-shaped sidewall spacers
CHARTERED SEMICONDUCTOR MFG45 citations91
US6228770B1May 8, 2001
Method to form self-sealing air gaps between metal interconnects
CHARTERED SEMICONDUCTOR MFG35 citations91
US6534393B1Mar 18, 2003
Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity
CHARTERED SEMICONDUCTOR MFG19 citations83