Inventor

CHEN CHIN-LONG

US64 patents

⚠️ This page may combine multiple inventors who share the name “CHEN CHIN-LONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN CHIN-LONG

IBM

Error correction coding of data blocks with included parity bits

Error correcting code retrofit method and apparatus for multiple memory configurations

Error correcting code retrofit method and apparatus for multiple memory configurations

Detecting address faults in an ECC-protected memory

Method and apparatus for bar code reading and decoding

Error correcting code for 8-bit-per-chip memory with reduced redundancy

Error propagation operating mode for error correcting code retrofit apparatus

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Low cost symbol error correction coding and decoding

(18, 9) Error correction code for double error correction and triple error detection

Method and apparatus for encoding special uncorrectable errors in an error correction code

Dual functioning symbol error correction code

Systematic symbol level ECC for use in digital memory systems

Low cost symbol error correction coding and decoding

Barcode scanner with adjustable light source intensity

Modular multiple error correcting code system

Error plus single bit error detection

Double error correction - triple error detection code

Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements

Extended error correction for SEC-DED codes with package error detection ability

Generating special uncorrectable error codes for failure isolation

Reduced gate error detection and correction circuit

Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address

Error detection and correction for four-bit-per-chip memory system

Memory implemented error detection and correction code with address parity bits

Dual level error detection and correction employing data subsets from previously corrected data

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

(146,130) error correction code utilizing address information

Memory card identification system

Single width bar code with end code providing bidirectionality

Extended error correction for package error correction codes

Fault tolerant system based on voting

Memory implemented error detection and correction code using memory modules

Presence/absence bar code

Method for writing single width bar codes on semiconductors wafers

Symbol level error correction codes which protect against memory chip and bus line failures

Circuits for calculating modular multiplicative inverse

Method for checking modular multiplication

Pipelining operations in a system for performing modular multiplication

Single symbol correction double symbol detection code employing a modular H-matrix

Method system and program products for error correction code conversion

Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (DQPSK)

Block-serial finite field multipliers

Dual error correction code

Method and apparatus for encoding certain double-error correcting and triple-error detecting codes

Method and apparatus for encoding certain double-error correcting and triple-error detecting codes

Method of correcting single errors

CHEN CHIN-LONG

Dumbbell assembly