Inventor

ALSUP MITCHELL

US36 patents

⚠️ This page may combine multiple inventors who share the name “ALSUP MITCHELL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALSUP MITCHELL

ADVANCED MICRO DEVICES INC

Stride-based prefetch mechanism using a prediction confidence value

System and method for validating a memory file that links speculative results of load operations to register values

Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system

Chained hybrid input/output memory management unit

Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots

Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation

System and method for handling exceptional instructions in a trace cache based processor

Cache memory system including a cache memory employing a tag including associated touch bits

System and method of identifying liveness groups within traces stored in a trace cache

Scheduler for use in a microprocessor that supports data-speculative execution

Method for proactive synchronization within a computer system

Controlling an I/O MMU

Avoiding silent data corruption and data leakage in a virtual environment with multiple guests

Microprocessor including cache memory supporting multiple accesses per cycle

Mapper circuit with backup capability

Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Cache memory subsystem including a fixed latency R/W pipeline

Method for denying probes during proactive synchronization within a computer system

Augmented instruction set for proactive synchronization within a computer system

Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)

Instruction cache prefetch based on trace cache eviction

Microprocessor including bank-pipelined cache with asynchronous data blocks

GLOBALFOUNDRIES INC

Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)

Virtualizing an IOMMU

Virtualizing an IOMMU

Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU)

System and method of implementing microcode operations as subroutines

MOTOROLA INC

Data processor for performing simultaneous instruction retirement and backtracking

Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic

Digital phase lock clock generator without local oscillator

Data processing system a method for performing register renaming having back-up capability

SAMSUNG ELECTRONICS CO LTD

Trace-based instruction execution processing

Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices

Micro-coded transcendental instruction execution

Control flow in a thread-based environment without branching

ALSUP MITCHELL

Transitioning from instruction cache to trace cache on label boundaries