Inventor

LAKSHMANAN VISWANATHAN

US17 patents

⚠️ This page may combine multiple inventors who share the name “LAKSHMANAN VISWANATHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAKSHMANAN VISWANATHAN

LSI LOGIC CORP

Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design

Method to translate UDPs using gate primitives

Method of partitioning an integrated circuit design for physical design verification

Method and apparatus for implementing engineering change orders

Verilog to vital translator

Method and computer program for verifying an incremental change to an integrated circuit design

Generating standard delay format files with conditional path delay for designing integrated circuits

Chip design method for designing integrated circuit chips with embedded memories

Method to debug IKOS method

Web based OLA memory generator

LSI CORP

Waiver mechanism for physical verification of system designs

N cell height decoupling circuit

Method of implementing an engineering change order in an integrated circuit design by windows

Incremental dummy metal insertions

Method of automating place and route corrections for an integrated circuit design from physical design validation

Unified layer stack architecture

LSI LOGIC CORPORTION

Method and system for layout versus schematic validation of integrated circuit designs