Inventor

KUO CHENG-CHENG

TW34 patents

⚠️ This page may combine multiple inventors who share the name “KUO CHENG-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO CHENG-CHENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Method for improving circuit layout for manufacturability

Vertical tunneling field-effect transistor cell and fabricating the same

Method for removing semiconductor fins using alternating masks

Vertical tunneling field-effect transistor cell and fabricating the same

Vertical tunneling field-effect transistor cell and fabricating the same

Metal gate features of semiconductor die

Vertical tunneling field-effect transistor cell and fabricating the same

Vertical tunneling field-effect transistor cell and fabricating the same

Vertical tunneling field-effect transistor cell with coaxially arranged gate contacts and drain contacts

Vertical tunneling field-effect transistor cell and fabricating the same

Method for improving circuit layout for manufacturability

Test circuit and method for operating the same

Vertical tunneling field-effect transistor cell

Vertical tunneling field-effect transistor cell and fabricating the same

Method for improving circuit layout for manufacturability

N/P boundary effect reduction for metal gate transistors

Method for line stress reduction through dummy shoulder structures

Method for removing semiconductor fins using alternating masks

TAIWAN SEMICONDUCTOR MFG

Vertical tunneling field-effect transistor cell and fabricating the same

Dummy patterns in integrated circuit fabrication

Dissection splitting with optical proximity correction and mask rule check enforcement

Vertical tunneling field-effect transistor cell and fabricating the same

Vertical tunneling field-effect transistor cell

Vertical tunneling field-effect transistor cell and fabricating the same

Revising layout design through OPC to reduce corner rounding effect

Regression system and methods for optical proximity correction modeling

Vertical tunneling field-effect transistor cell and fabricating the same

Vertical tunneling field-effect transistor cell and fabricating the same

N/P boundary effect reduction for metal gate transistors

CHUANG HAK-LAY

N/P boundary effect reduction for metal gate transistors

KUO CHENG CHENG

Dummy shoulder structure for line stress reduction

KUO CHENG-CHENG

Optical proximity correction convergence control

HO JENG-SHIUN

Sub-resolution rod in the transition region

CHUANG HARRY-HAK-LAY

Controlling gate formation for high density cell layout