Inventor
REYNAUD PATRICK
FR19 patents
⚠️ This page may combine multiple inventors who share the name “REYNAUD PATRICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SOITEC SILICON ON INSULATOR
10 patentsUS7405136B2Jul 29, 2008
Methods for manufacturing compound-material wafers and for recycling used donor substrates
SOITEC SILICON ON INSULATOR25 citations91
US9293473B2Mar 22, 2016
Method for manufacturing a semiconductor on insulator structure having low electrical losses
SOITEC SILICON ON INSULATOR8 citations84
US7413964B2Aug 19, 2008
Method of revealing crystalline defects in a bulk substrate
SOITEC SILICON ON INSULATOR14 citations84
US8962450B2Feb 24, 2015
Method for manufacturing a semiconductor-on-insulator structure having low electrical losses
SOITEC SILICON ON INSULATOR5 citations82
US7736994B2Jun 15, 2010
Method for manufacturing compound material wafers and corresponding compound material wafer
SOITEC SILICON ON INSULATOR9 citations81
US7892861B2Feb 22, 2011
Method for fabricating a compound-material wafer
SOITEC SILICON ON INSULATOR2 citations62
US11373856B2Jun 28, 2022
Support for a semiconductor structure
SOITEC SILICON ON INSULATOR0 citations60
US7718534B2May 18, 2010
Planarization of a heteroepitaxial layer
SOITEC SILICON ON INSULATOR4 citations58
US9698063B2Jul 4, 2017
Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure
SOITEC SILICON ON INSULATOR0 citations36
US9653536B2May 16, 2017
Method for fabricating a structure
SOITEC SILICON ON INSULATOR0 citations33
COMMISSARIAT ENERGIE ATOMIQUE
3 patentsUS10107772B2Oct 23, 2018
Electronical device for measuring at least one electrical characteristic of an object
COMMISSARIAT ENERGIE ATOMIQUE3 citations62
US10204786B2Feb 12, 2019
Device for connecting at least one nano-object and method of manufacturing it
COMMISSARIAT ENERGIE ATOMIQUE0 citations48
US10858244B2Dec 8, 2020
Device for connecting at least one nano-object associated with a chip enabling a connection to at least one external electrical system and method of fabrication thereof
COMMISSARIAT ENERGIE ATOMIQUE0 citations37
REYNAUD PATRICK
3 patentsUS8658514B2Feb 25, 2014
Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure
REYNAUD PATRICK1 citations60
US8962492B2Feb 24, 2015
Method to thin a silicon-on-insulator substrate
REYNAUD PATRICK1 citations47
US9244019B2Jan 26, 2016
Method for measuring defects in a silicon substrate by applying a heat treatment which consolidates and enlarges the defects
REYNAUD PATRICK0 citations36