Inventor
O'RIORDAN DONALD J
US40 patents
⚠️ This page may combine multiple inventors who share the name “O'RIORDAN DONALD J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
21 patentsUS6381563B1Apr 30, 2002
System and method for simulating circuits using inline subcircuits
CADENCE DESIGN SYSTEMS INC52 citations94
US8683400B1Mar 25, 2014
System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
CADENCE DESIGN SYSTEMS INC24 citations90
US7367006B1Apr 29, 2008
Hierarchical, rules-based, general property visualization and editing method and system
CADENCE DESIGN SYSTEMS INC32 citations86
US9047424B1Jun 2, 2015
System and method for analog verification IP authoring and storage
CADENCE DESIGN SYSTEMS INC8 citations84
US9032347B1May 12, 2015
System and method for automated simulator assertion synthesis and digital equivalence checking
CADENCE DESIGN SYSTEMS INC9 citations84
US9009635B1Apr 14, 2015
System and method for simulator assertion synthesis and digital equivalence checking
CADENCE DESIGN SYSTEMS INC13 citations84
US9589085B1Mar 7, 2017
Systems and methods for viewing analog simulation check violations in an electronic design automation framework
CADENCE DESIGN SYSTEMS INC8 citations82
US9026963B1May 5, 2015
System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
CADENCE DESIGN SYSTEMS INC7 citations82
US8832612B1Sep 9, 2014
Netlisting analog/mixed-signal schematics to VAMS
CADENCE DESIGN SYSTEMS INC6 citations81
US8813004B1Aug 19, 2014
Analog fault visualization system and method for circuit designs
CADENCE DESIGN SYSTEMS INC7 citations81
US10445290B1Oct 15, 2019
System and method for a smart configurable high performance interactive log file viewer
CADENCE DESIGN SYSTEMS INC8 citations80
US8875077B1Oct 28, 2014
Fault sensitivity analysis-based cell-aware automated test pattern generation flow
CADENCE DESIGN SYSTEMS INC16 citations79
US7085700B2Aug 1, 2006
Method for debugging of analog and mixed-signal behavioral models during simulation
CADENCE DESIGN SYSTEMS INC20 citations79
US9245088B1Jan 26, 2016
System and method for data mining safe operating area violations
CADENCE DESIGN SYSTEMS INC4 citations73
US9501598B1Nov 22, 2016
System and method for assertion publication and re-use
CADENCE DESIGN SYSTEMS INC4 citations71
US9213787B1Dec 15, 2015
Simulation based system and method for gate oxide reliability enhancement
CADENCE DESIGN SYSTEMS INC5 citations71
US8863050B1Oct 14, 2014
Efficient single-run method to determine analog fault coverage versus bridge resistance
CADENCE DESIGN SYSTEMS INC6 citations67
US9038008B1May 19, 2015
System and method for containing analog verification IP
CADENCE DESIGN SYSTEMS INC2 citations60
US9020277B1Apr 28, 2015
Image-based stimulus for circuit simulation
CADENCE DESIGN SYSTEMS INC1 citations50
US10223484B1Mar 5, 2019
Spice model bin inheritance mechanism
CADENCE DESIGN SYSTEMS INC0 citations39
US8996348B1Mar 31, 2015
System and method for fault sensitivity analysis of digitally-calibrated-circuit designs
CADENCE DESIGN SYSTEMS INC0 citations36
O'RIORDAN DONALD J
10 patentsUS9182948B1Nov 10, 2015
Method and system for navigating hierarchical levels using graphical previews
O'RIORDAN DONALD J38 citations94
US8838559B1Sep 16, 2014
Data mining through property checks based upon string pattern determinations
O'RIORDAN DONALD J12 citations84
US8689121B2Apr 1, 2014
System and method for management of controls in a graphical user interface
O'RIORDAN DONALD J14 citations84
US8214791B1Jul 3, 2012
User interface for inherited connections in a circuit
O'RIORDAN DONALD J10 citations84
US9355130B1May 31, 2016
Method and system for component parameter management
O'RIORDAN DONALD J7 citations83
US8949203B1Feb 3, 2015
Verification of design libraries and databases
O'RIORDAN DONALD J15 citations81
US8601412B1Dec 3, 2013
Netlisting analog/mixed-signal schematics to VAMS
O'RIORDAN DONALD J6 citations81
US8176463B2May 8, 2012
Modeling and simulating device mismatch for designing integrated circuits
O'RIORDAN DONALD J8 citations77
US8954307B1Feb 10, 2015
Chained programming language preprocessors for circuit simulation
O'RIORDAN DONALD J4 citations71
US8296717B1Oct 23, 2012
Method and system for implementing inherited connections for electronics designs
O'RIORDAN DONALD J2 citations62
MAJUMDER CHAYAN
4 patentsUS8438531B2May 7, 2013
Visualization and information display for shapes in displayed graphical images
MAJUMDER CHAYAN5 citations70
US8711177B1Apr 29, 2014
Generation, display, and manipulation of measurements in computer graphical designs
MAJUMDER CHAYAN2 citations61
US8645901B2Feb 4, 2014
Visualization and information display for shapes in displayed graphical images based on a cursor
MAJUMDER CHAYAN3 citations60
US8533626B2Sep 10, 2013
Visualization and information display for shapes in displayed graphical images based on user zone of focus
MAJUMDER CHAYAN2 citations60
GINETTI ARNOLD
2 patentsUS8762906B2Jun 24, 2014
Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation
GINETTI ARNOLD23 citations91
US8732636B2May 20, 2014
Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation
GINETTI ARNOLD23 citations91