Inventor
WOOD MICHAEL H
US34 patents
⚠️ This page may combine multiple inventors who share the name “WOOD MICHAEL H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS6177708B1Jan 23, 2001
SOI FET body contact structure
IBM246 citations97
US7073112B2Jul 4, 2006
Compilable address magnitude comparator for memory array self-testing
IBM19 citations92
US6658610B1Dec 2, 2003
Compilable address magnitude comparator for memory array self-testing
IBM23 citations92
US6154091ANov 28, 2000
SOI sense amplifier with body contact structure
IBM30 citations90
US9495497B1Nov 15, 2016
Dynamic voltage frequency scaling
IBM10 citations84
US9483604B1Nov 1, 2016
Variable accuracy parameter modeling in statistical timing
IBM9 citations84
US9418198B1Aug 16, 2016
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
IBM4 citations72
US5563517AOct 8, 1996
Dual channel d.c. low noise measurement system and test methodology
IBM10 citations72
US5434385AJul 18, 1995
Dual channel D.C. low noise measurement system and test methodology
IBM6 citations72
US9910954B2Mar 6, 2018
Programmable clock division methodology with in-context frequency checking
IBM2 citations70
US9934341B2Apr 3, 2018
Simulation of modifications to microprocessor design
IBM2 citations69
US8589842B1Nov 19, 2013
Device-based random variability modeling in timing analysis
IBM4 citations62
US8799846B1Aug 5, 2014
Facilitating the design of a clock grid in an integrated circuit
IBM2 citations57
US9646122B2May 9, 2017
Variable accuracy parameter modeling in statistical timing
IBM1 citations52
US8984261B2Mar 17, 2015
Store data forwarding with no memory model restrictions
IBM0 citations52
US8930864B2Jan 6, 2015
Method of sharing and re-using timing models in a chip across multiple voltage domains
IBM1 citations52
US7681169B2Mar 16, 2010
Process for managing complex pre-wired net segments in a VLSI design
IBM1 citations52
US9727687B2Aug 8, 2017
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
IBM0 citations51
US9607124B2Mar 28, 2017
Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints
IBM1 citations51
US10354046B2Jul 16, 2019
Programmable clock division methodology with in-context frequency checking
IBM0 citations49
US8954914B2Feb 10, 2015
Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design
IBM1 citations49
US9928322B2Mar 27, 2018
Simulation of modifications to microprocessor design
IBM0 citations48
US9710594B2Jul 18, 2017
Variation-aware timing analysis using waveform construction
IBM0 citations40
US10372851B2Aug 6, 2019
Independently projecting a canonical clock
IBM0 citations38
US10691853B2Jun 23, 2020
Superposition of canonical timing value representations in statistical static timing analysis
IBM0 citations33