Inventor

WU XUSHENG

US118 patents

⚠️ This page may combine multiple inventors who share the name “WU XUSHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU XUSHENG

GLOBALFOUNDRIES INC

Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product

Vertical field effect transistor formation with critical dimension control

Methods, apparatus and system for gate cut process using a stress material in a finFET device

Low-K dielectric spacer for a gate cut

Methods of cutting gate structures on transistor devices

Devices and methods of improving device performance through gate cut last process

Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices

Multi-phase source/drain/gate spacer-epi formation

Fin-type field effect transistors with single-diffusion breaks and method

Product comprised of FinFET devices with single diffusion break isolation structures

T-shaped single diffusion barrier with single mask approach process flow

Methods of forming replacement gate structures on transistor devices

Metal-insulator-metal capacitors with enlarged contact areas

Multiple Fin heights with dielectric isolation

FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same

Methods for performing a gate cut last scheme for FinFET semiconductor devices

Dielectric preservation in a replacement gate process

Nanowire transistors having multiple threshold voltages

Vertical field effect transistor

Self-aligned deep contact for vertical FET

Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device

Method to make gate-to-body contact to release plasma induced charging

Fabricating fin structures with doped middle portions

Method and structure to provide integrated long channel vertical FinFET device

Method of forming mandrel and non-mandrel metal lines having variable widths

Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same

Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Fin-type field effect transistors with single-diffusion breaks and method

Preventing bridge formation between replacement gate and source/drain region through STI structure

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Methods for crossed-fins FinFET device for sensing and measuring magnetic fields

Transistor structures and fabrication methods thereof

Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices

T-shaped contacts for semiconductor device

Methods for forming FinFETs with reduced series resistance

Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

Epi facet height uniformity improvement for FDSOI technologies

Fin structure in sublitho dimension for high performance CMOS application

Forming self-aligned NiSi placement with improved performance and yield

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device structure with metal gate stack

Semiconductor device with air spacer and stress liner

Semiconductor device with corner isolation protection and methods of forming the same

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Devices with strained isolation features

Semiconductor device with air gaps between metal gates and method of forming the same

Air gap seal for interconnect air gap and method of fabricating thereof

UNIV HONG KONG SCIENCE & TECHN

Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits