P

Inventor

HELLER LISA C

US116 patents
⚠️ This page may combine multiple inventors who share the name “HELLER LISA C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

30 patents
US7197601B2Mar 27, 2007

Method, system and program product for invalidating a range of selected storage translation table entries

IBM81 citations99
US7284100B2Oct 16, 2007

Invalidating storage, clearing buffer entries, and an instruction therefor

IBM74 citations98
US5317754AMay 31, 1994

Method and apparatus for enabling an interpretive execution subset

IBM109 citations97
US6996698B2Feb 7, 2006

Blocking processing restrictions based on addresses

IBM51 citations96
US5465374ANov 7, 1995

Processor for processing data string by byte-by-byte

IBM131 citations96
US8935504B1Jan 13, 2015

Execution of a perform frame management function instruction

IBM11 citations93
US8909899B2Dec 9, 2014

Emulating execution of a perform frame management instruction

IBM22 citations93
US8380907B2Feb 19, 2013

Method, system and computer program product for providing filtering of GUEST2 quiesce requests

IBM25 citations93
US8041923B2Oct 18, 2011

Load page table entry address instruction execution based on an address translation format control field

IBM25 citations93
US9697135B2Jul 4, 2017

Suppressing virtual address translation utilizing bits and instruction tagging

IBM17 citations92
US9330018B2May 3, 2016

Suppressing virtual address translation utilizing bits and instruction tagging

IBM22 citations92
US9330017B2May 3, 2016

Suppressing virtual address translation utilizing bits and instruction tagging

IBM19 citations92
US9092382B2Jul 28, 2015

Reducing microprocessor performance loss due to translation table coherency in a multi-processor system

IBM22 citations92
US9069715B2Jun 30, 2015

Reducing microprocessor performance loss due to translation table coherency in a multi-processor system

IBM17 citations92
US8387049B2Feb 26, 2013

Facilitating processing within computing environments supporting pageable guests

IBM21 citations92
US8032716B2Oct 4, 2011

System, method and computer program product for providing a new quiesce state

IBM20 citations92
US7530067B2May 5, 2009

Filtering processor requests based on identifiers

IBM17 citations92
US7281115B2Oct 9, 2007

Method, system and program product for clearing selected storage translation buffer entries

IBM14 citations92
US7020761B2Mar 28, 2006

Blocking processing restrictions based on page indices

IBM26 citations92
US5619715AApr 8, 1997

Hardware implementation of string instructions

IBM33 citations90
US5608887AMar 4, 1997

Method of processing data strings

IBM29 citations90
US11150905B2Oct 19, 2021

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

IBM4 citations84
US10241910B2Mar 26, 2019

Creating a dynamic address translation with translation exception qualifiers

IBM8 citations84
US10078585B2Sep 18, 2018

Creating a dynamic address translation with translation exception qualifiers

IBM6 citations84
US9454490B2Sep 27, 2016

Invalidating a range of two or more translation table entries and instruction therefore

IBM5 citations84
US9354873B2May 31, 2016

Performing a clear operation absent host intervention

IBM3 citations84
US9092351B2Jul 28, 2015

Creating a dynamic address translation with translation exception qualifier

IBM9 citations84
US8806178B2Aug 12, 2014

Set sampling controls instruction

IBM6 citations84
US8041922B2Oct 18, 2011

Enhanced dynamic address translation with load real address function

IBM10 citations84
US8037278B2Oct 11, 2011

Dynamic address translation with format control

IBM15 citations84

GREINER DAN F

11 patents

BARTIK JANE H

3 patents

HELLER LISA C

2 patents

SLEGEL TIMOTHY J

1 patent

ALEXANDER GREGORY W

1 patent

BLANDY GEOFFREY O

1 patent

INTERNAT BUISNESS MACHINES CORP

1 patent

Showing the top 50 of 116 patents by PatentIndex Score.