P

Inventor

LEHNERT FRANK

DE42 patents
⚠️ This page may combine multiple inventors who share the name “LEHNERT FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

26 patents
US10380033B2Aug 13, 2019

Multi-engine address translation facility

IBM6 citations84
US6766434B2Jul 20, 2004

Method for sharing a translation lookaside buffer between CPUs

IBM18 citations84
US10380032B2Aug 13, 2019

Multi-engine address translation facility

IBM1 citations73
US10083124B1Sep 25, 2018

Translating virtual memory addresses to physical addresses

IBM6 citations73
US10025608B2Jul 17, 2018

Quiesce handling in multithreaded environments

IBM4 citations73
US9207706B2Dec 8, 2015

Generating monotonically increasing TOD values in a multiprocessor system

IBM3 citations63
US11036647B2Jun 15, 2021

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations62
US10956341B2Mar 23, 2021

Multi-engine address translation facility

IBM0 citations62
US10929312B2Feb 23, 2021

Zone-SDID mapping scheme for TLB purges

IBM0 citations62
US10635603B2Apr 28, 2020

Multi-engine address translation facility

IBM0 citations52
US10621105B2Apr 14, 2020

Multi-engine address translation facility

IBM0 citations52
US10353827B2Jul 16, 2019

Zone-SDID mapping scheme for TLB purges

IBM0 citations52
US10353828B2Jul 16, 2019

Zone-SDID mapping scheme for TLB purges

IBM0 citations52
US10176002B2Jan 8, 2019

Quiesce handling in multithreaded environments

IBM0 citations52
US9760511B2Sep 12, 2017

Efficient interruption routing for a multithreaded processor

IBM1 citations52
US9715458B2Jul 25, 2017

Multiprocessor computer system

IBM1 citations52
US9678830B2Jun 13, 2017

Recovery improvement for quiesced systems

IBM0 citations52
US9665424B2May 30, 2017

Recovery improvement for quiesced systems

IBM0 citations52
US9658852B2May 23, 2017

Updating of shadow registers in N:1 clock domain

IBM1 citations52
US10698835B2Jun 30, 2020

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US10387326B2Aug 20, 2019

Incorporating purge history into least-recently-used states of a translation lookaside buffer

IBM0 citations51
US10353825B2Jul 16, 2019

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US10289562B2May 14, 2019

Incorporating purge history into least-recently-used states of a translation lookaside buffer

IBM0 citations51
US10248575B2Apr 2, 2019

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US9311137B2Apr 12, 2016

Delaying interrupts for a transactional-execution facility

IBM0 citations41
US7650535B2Jan 19, 2010

Array delete mechanisms for shipping a microprocessor with defective arrays

IBM0 citations39

BELIMO HOLDING AG

5 patents

RUETI AG MASCHF

3 patents

LEHNERT FRANK

2 patents

CREMER MICHAEL

2 patents

SULZER RUTI AG

1 patent

NIEDERHAUSER URS

1 patent

MAYER ULRICH

1 patent

BRUKER BIOSPIN AG

1 patent